Wu, Wuxi

Aijun Wu, Wuxi CN

Patent application number	Description	Published
20150144615	BRAZING METHOD AND DEVICE FOR GLASS KOVAR COMBINATION AND OXYGEN-FREE COPPER - The invention discloses a brazing method for a glass Kovar combination and an oxygen-free copper, wherein the glass Kovar combination, the silver-based solder and the oxygen-free copper are placed within a quartz room with the pressure of 3.0×10	05-28-2015

Haiqiang Wu, Wuxi CN

Patent application number	Description	Published
20120285833	PREPARATION METHOD FOR MOLECULAR RECOGNITION SENSOR BY ELECTRODEPOSITION - A preparation method for molecular recognition sensor by electrodeposition is provided. The preparation method is as following: forming molecularly imprinted polymeric micelles by self-assembly of ionic type photosensitive copolymers; forming a film on the surface of an electrode by electrodepositing the molecularly imprinted polymeric micelles at a constant potential; crosslinking the electrodeposited micellar film via ultraviolet light irradiation; extracting the template molecules from the crosslinked film to obtain electrode modified by the molecularly imprinted polymeric micellar film; and connecting the modified electrode with a sensor device and a computer to construct a molecular recognition sensing system capable of specifically detecting the template molecules.	11-15-2012

Hsiaochia Wu, Wuxi CN

Patent application number	Description	Published
20130099327	CMOS DEVICES AND METHOD FOR MANUFACTURING THE SAME - A complementary metal-oxide semiconductor (CMOS) device is disclosed. The CMOS device includes a substrate, a well region formed in the substrate, and a gate formed on the substrate. The CMOS device also includes a first region and a second region formed in the well region and arranged at two sides of the gate. Further, the CMOS device includes a first light-doped drain (LDD) region and a second LDD region formed in the well region and extending the first region and the second region, respectively, towards the gate. The CMOS device also includes a first doped layer formed in the first LDD region, and a conduction type of an ion doped in the first doped layer is opposite to a conduction type of an ion doped in the first LDD region.	04-25-2013
20140159151	Power MOS Device Structure - Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.	06-12-2014

Hsiao-Chia Wu, Wuxi CN

Patent application number	Description	Published
20130134562	SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR BURIED LAYER - The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects.	05-30-2013

Lizhong Wu, Wuxi CN

Patent application number	Description	Published
20120024350	Photovoltaic module frame and a photovoltaic module having the frame - This invention discloses a photovoltaic module comprising a photovoltaic module panel and a plurality of photovoltaic module frame segments adapted for holding the photovoltaic module therein; each of the photovoltaic module frame segments comprises a base wall, a photovoltaic module holding part and a first side wall extending between the base wall and the photovoltaic module holding part; the photovoltaic module holding part has a recess facing toward a first direction, the photovoltaic module holding part defines an upper face and a bottom face opposite to each other, wherein said first side wall is oriented at an obtuse angle relative to the bottom face of the photovoltaic module holding part. The advantageous effects of this invention are: the simple structure and the unique configuration of the frame can realize the stable stacking and the fast and stable assembly of the photovoltaic modules and improve the space efficiency when packaging and transporting, thereby reducing the packaging and transporting costs.	02-02-2012

Pengpeng Wu, Wuxi CN

Patent application number	Description	Published
20130196489	METHOD FOR MANUFACTURING DEEP-TRENCH SUPER PN JUNCTIONS - The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.	08-01-2013

Si-Min Wu, Wuxi CN

Patent application number	Description	Published
20120038391	TRANSISTOR MODULE AND TRANSISTOR DRIVING MODULE - The present invention discloses a transistor driving module, coupling to a converting controller, to driving a high side transistor and a low side transistor connected in series, wherein one end of the high side transistor is coupled to an input voltage and one end of the low side transistor is grounded. The transistor driving module comprises a high side driving unit, a low side driving unit, a current limiting unit and an anti-short through unit. The high side driving unit generates a high side driving signal to turn the high side transistor on according to a duty cycle signal, and the low side driving unit generates a low side driving signal turn the low side transistor on according to the high side driving signal. The current limiting unit is coupled to the high side transistor and the high side driving unit, and generates a current limiting signal when a current flowing through the high side transistor higher than a current limiting value. The high side driving unit is stopped to generate the high side driving signal when receiving the current limiting value. The anti-short through unit is coupled to the high side driving unit and the low side driving unit to control the generations of the high side driving signal and the low side driving signal to have the timings of the high side driving signal and the low side driving signal non-overlapped.	02-16-2012
20120319754	TRANSISTOR SWITCH CONTROL CIRCUIT - A synchronous driving circuit in the arts may cause a short through pheromone when a duty cycle of a duty cycle control signal is too short. The present invention sets a delay time with a suitable period when the duty cycle of the duty cycle control signal is too short to avoid the short through phenomenon.	12-20-2012

Tzong Shiann Wu, Wuxi CN

Patent application number	Description	Published
20130196489	METHOD FOR MANUFACTURING DEEP-TRENCH SUPER PN JUNCTIONS - The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.	08-01-2013

Xiangchang Wu, Wuxi CN

Patent application number	Description	Published
20120298834	MACHINE AND FIXED CONNECTION OF OPERATING SPACE FRAME FOR THE SAME - The present disclosure discloses a fixed connection of an operating space frame of a machine, comprising: a machine frame; an operating space frame mounted on the machine frame and having a plurality of posts, wherein a first connecting plate is fixedly connected respectively at a lower portion of at least two adjacent posts, the first mounting plate is fixedly connected to the machine frame via a connecting member, and a stopper is provided between the first mounting plate and the machine frame. The fixed connection improves the connection strength between the operating space frame and the machine so as to suppress deformation of the operating space frame subjected to an impact of an external force and thus provide protection for the operator and equipments therein. The present disclosure further relates to a machine having the above fixed connection.	11-29-2012

Xiaojiang Wu, Wuxi CN

Patent application number	Description	Published
20120188031	Programmable high-frequency high-gain equalizer for digital display interfaces - There is provided a programmable high-frequency high-gain equalizer for digital display interfaces comprising, two pairs of current sources; two pairs of transistors arranged as two differential pairs, each transistor connected to a different one of the current sources; and a pair of a negative impedance resistors connected to the two pairs of two differential pairs; and a pair of capacitive and programmable resistive degeneration connected to the two pairs of two differential pairs to optimize the equalizer gain.	07-26-2012