Patent application number | Description | Published |
20100176413 | LIGHT-EMITTING DIODE DEVICE INCLUDING A MULTI-FUNCTIONAL LAYER - A light-emitting diode device includes: a substrate; a light-emitting layered structure formed on the substrate; a multi-functional layer having a first main portion and formed on the light-emitting layered structure for spreading current laterally and for reflecting light emitted from the light-emitting layered structure; and first and second electrodes electrically coupled to the light-emitting layered structure. The first electrode is formed on the light-emitting layered structure and has a first electrode main part. The first main portion of the multi-functional layer is aligned below and is provided with a size larger than that of the first electrode main part. | 07-15-2010 |
20100178616 | METHOD OF MAKING A ROUGH SUBSTRATE - A method of making a rough substrate includes: (a) forming a first oxide layer; (b) coating a photoresist layer; (c) exposing and developing the photoresist layer; (d) etching parts of the first oxide layer such that parts of the first oxide layer are formed into a plurality of sacrificial protrusions; (e) removing the photoresist regions; (f) depositing on the substrate layer and the sacrificial protrusions a second oxide layer; (g) etching the second oxide layer so as to leave portions of the second oxide layer; and (h) etching additionally the sacrificial protrusions, the substrate layer, and the portions of the second oxide layer, thereby producing a plurality of flat recess bottom faces, and substrate protrusions. | 07-15-2010 |
20100320478 | LIGHT-EMITTING DIODE DEVICE INCLUDING A CURRENT BLOCKING REGION AND METHOD OF MAKING THE SAME - A light-emitting diode device includes: a substrate; a light-emitting layered structure disposed on the substrate and including a first cladding layer, an active layer, and a second cladding layer; a first electrode; a second electrode disposed on the light-emitting layered structure; and a current blocking region provided in the light-emitting layered structure below the second electrode, and having a main portion that is aligned below and is as large as the second electrode, and an extension portion extending from the main portion and protruding beyond the second electrode to a distance ranging from 3 μm to 20 μm. | 12-23-2010 |
20100320498 | LIGHT-EMITTING DIODE DEVICE - A light-emitting diode device includes: a substrate; and a semiconductor layered structure including an n-type semiconductor layer that has an exposed region, and a p-type semiconductor layer that is disposed over the n-type semiconductor layer without extending over the exposed region. An electrode unit is electrically coupled to the semiconductor layered structure, and includes a first electrode and a second electrode. The second electrode has an electrode pad, an end node, and a connecting strip. The electrode pad is larger than the end node. The connecting strip is narrower than the end node. | 12-23-2010 |
Patent application number | Description | Published |
20090102854 | DISPLAY METHOD AND COLOR SEQUENTIAL DISPLAY - A display method and a color sequential display using the same are provided. The color sequential display displays a frame in a frame period, wherein the frame includes a plurality of sub-frames, and the frame period includes a plurality of sub-frame periods. In the display method, a first sub-frame is displayed in response to a luminaire device during a first sub-frame period, and in simultaneous, a second sub-frame is addressed in the first sub-frame period. Next, the second sub-frame is displayed in response to the luminaire device during a second sub-frame period. In the display method, scales of the first sub-frame period and the second sub-frame period are determined according to the luminous efficiency of the luminaire device. Therefore, the optical performance of the color sequential display can be enhanced. | 04-23-2009 |
20090102867 | DISPLAY METHOD - A display method for a color sequential display to display a frame in a frame time is provided. The frame time includes a first sub-frame time and a second sub-frame time, and the frame includes a first sub-frame and a second sub-frame. The display method includes displaying the first sub-frame in the first sub-frame time which is divided into a first liquid crystal (LC) response time and a first optical display time. In addition, the second sub-frame is displayed in the second sub-frame time which is divided into a second LC response time and a second optical display time. The scales of the first sub-frame time and the second sub-frame time are different from each other according to a default value. The display method improves the optical performance of the color sequential display. | 04-23-2009 |
20090135205 | DISPLAY METHOD FOR COLOR SEQUENTIAL DISPLAY - A display method for a color sequential display is disclosed. The display method includes following steps. First, a frame is displayed by four color signals of a red signal, a green signal, a blue signal and a compensation signal. Next, a frame period is divided into eight subframe periods according to a sequence. Next, three of the said four color signals are selected and arranged in a sequence. And then, the selected three color signals are respectively displayed at the first, the second and the third subframe periods according to the sequence and respectively displayed at the fourth, the fifth and the sixth subframe periods according to the same sequence. After that, the unselected color signal of the said four color signals is displayed at the seventh and the eighth subframe periods. | 05-28-2009 |
Patent application number | Description | Published |
20080303174 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 12-11-2008 |
20090189296 | FLIP CHIP QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE - A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads. | 07-30-2009 |
20090206459 | QUAD FLAT NON-LEADED PACKAGE STRUCTURE - A quad flat non-leaded package structure including a die pad, a plurality of leads, a chip, and a molding compound is provided. The die pad has a top surface and an opposite bottom surface, and the leads are disposed around the die pad. A concave portion is disposed at the end of each leads. The chip is disposed on the top surface of the die pad and is electrically connected to the leads. The molding compound encapsulates the chip, a portion of the leads and the die pad, and fills the gaps between the leads. | 08-20-2009 |
20100187691 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 07-29-2010 |
20100187692 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 07-29-2010 |
20100264540 | IC Package Reducing Wiring Layers on Substrate and Its Carrier - An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed. | 10-21-2010 |
Patent application number | Description | Published |
20090020316 | METHOD OF MANUFACTURING CHIP ON FILM AND STRUCTURE THEREOF - A method of manufacturing a chip on film (COF) is provided, including: providing a flexible circuit board; and forming a plurality of leads on the flexible circuit board. Each of the leads has a thickness of 8 um˜15 um and a cross-section shape is substantially rectangular. A COF structure, having a flexible circuit board and a plurality of leads formed on the flexible circuit board, is provided. Each lead has a thickness of 8 um˜15 um, and lead widths of the leads are based on pitch widths of a plurality of bumps corresponding to the leads. A COF structure, having a flexible circuit board and a plurality of leads formed on the flexible circuit board. Each of the leads has a thickness of 8 um˜15 um, and a lead width of each of the leads is greater than a bump width minus 4 um. | 01-22-2009 |
20090091028 | SEMICONDUCTOR DEVICE AND METHOD OF BUMP FORMATION - A semiconductor device including a semiconductor substrate, a contact pad, a passivation layer, a bump, and a seeding layer is provided. The semiconductor substrate has an active surface. The contact pad is disposed on the active surface. The passivation layer is disposed on the active surface and exposes a central part of the contact pad. The seeding layer is disposed on the exposed central part of the contact pad. The bump has a top surface, a bottom surface opposite to the top surface, and a side surface connecting the top surface and the bottom surface. The bump is disposed on the seeding layer. The bump is placed in contact with the seeding layer by the bottom surface and by part of the side surface. | 04-09-2009 |
20090218116 | BUILT-IN METHOD OF THERMAL DISSIPATION LAYER FOR DRIVER IC SUBSTRATE AND STRUCTURE THEREOF - A chip on film (COF) structure includes a flexible circuit board and a chip. The flexible circuit board includes a flexible base film and a conductive layer. The flexible base film has a polyimide layer and an anisotropic conductive layer (ACL). The conductive layer is disposed on the flexible base film. The conductive layer and the ACL are separated by the polyimide layer. The chip is mounted with the conductive layer via interconnectors. | 09-03-2009 |
Patent application number | Description | Published |
20100295865 | DISPLAY METHOD AND COLOR SEQUENTIAL DISPLAY - A color sequential display and a display method using the same are provided. The color sequential display displays a frame in a frame period. The frame includes a plurality of sub-frames. The frame period includes a plurality of sub-frame periods corresponding to the sub-frames. In the display method, a first color light source is turned on according to a first duty cycle within a first sub-frame period for displaying a first sub-frame. Next, a second color light source is turned on according to a second duty cycle within a second sub-frame period for displaying a second sub-frame. Finally, the first color light source and the second color light source are respectively turned on according to a first modified duty cycle and a second modified duty cycle. The first modified duty cycle and the second modified duty cycle are proportioned to the first and the second duty cycles. | 11-25-2010 |
20110058132 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a display device is provided. Firstly, an active device array substrate having an active surface is provided. Next, a first patterned photoresist layer is formed on the active surface. Then, a first alignment layer is obliquely vapor-deposited on the active surface and the first patterned photoresist layer, wherein the active surface comprises at least a first undeposited area located beside an edge of the first patterned photoresist layer. A first alignment unit is formed by removing the first patterned photoresist layer and a portion of the first alignment layer located thereon. A sealant is directly formed on the active surface of the active device array substrate and surrounds the first alignment unit. An opposite substrate having a light transmissive surface is provided. After that, the active device array substrate and the opposite substrate are assembled. A display device is also provided. | 03-10-2011 |
20120019565 | METHOD FOR DRIVING REFLECTIVE LCD PANEL - A method for driving a reflective LCD panel is provided. The driving method includes following steps: the reflective LCD panel is driven by a driving signal with alternate positive and negative polarities, wherein the driving signal has positive polarity for a first driving duration and the driving signal has negative polarity for a second driving duration; a color beam is provided to irradiate the reflective LCD panel during a partial time period of the first driving duration; and the color beam is provided to irradiate the reflective LCD panel during a partial time period of the second driving duration. | 01-26-2012 |
20120120355 | STRUCTURE OF REFLECTIVE DISPLAY PANEL - A structure of a reflective display panel including a silicon substrate, a liquid crystal layer and a stacked compensation film layer is provided. The liquid crystal layer disposed on the silicon substrate has a first phase retardation which is within a first retardation range. The stacked compensation film layer disposed on the liquid crystal layer has a second phase retardation which is within a second retardation range. The stacked compensation film layer is selected according to an optical characteristic of the liquid crystal layer so as to increase a contrast of the reflective display panel. | 05-17-2012 |
Patent application number | Description | Published |
20110176313 | OPTICAL UNIT AND LIGHT GUIDE PLATE AND INK THEREOF - The present invention relates to an optical unit and light guide plate and ink thereof. The ink includes a base resin and a plurality of fine particles. The base resin has a first refractive index. The fine particles have a second refractive index and are dispersed in the base resin. The fine particles are made of organic polymer. The difference between the first refractive index and second refractive index is less than 0.15. The use of the ink will lower the color difference and the variation of color temperature of the light guide plate or the optical unit. | 07-21-2011 |
20110199783 | Light Guide Plate and Back Light Module Having the Same - The present invention relates to a light guide plate and back light module having the same. The light guide plate includes a light guide plate body and a plurality of microreliefs. The light guide plate body has a light-emitting surface and a reflecting surface. The microreliefs are disposed on the reflecting surface. Each of the microreliefs has an outer surface and a base area. The outer surface is a curved surface, and the base area contacts the reflecting surface. A ratio of the totally height of each of the microreliefs to the diameter of the base area of each of the microreliefs is between 1/7 and ¼. As a result, the light guide plate has higher light extraction efficiency. | 08-18-2011 |
20110199785 | Backlight Module, Light Guide Plate Thereof and Ink Thereof - The present invention relates to a backlight module, light guide plate thereof and ink thereof. The ink includes a base resin and an additive. The additive is dispersed in the base resin for increasing the printability of the ink. The additive comprises a polymer having hydroxy functional group, ester functional group, ether functional group or combination thereof. Use of the ink of the present invention will reduce the color difference and the variation of color temperature of the light guide plate. In addition, the ink has higher flowability, which increases the printability of the ink. | 08-18-2011 |
20120120679 | BACKLIGHT MODULE, LIGHT GUIDE PLATE THEREOF AND INK THEREOF - The present invention relates to a light guide plate and ink thereof. The ink includes a base resin and a plurality of hollow structures. The hollow structures are dispersed in the base resin and comprise air therein. In the present invention, the hollow structures in the ink give the light guide plate higher light extraction efficiency. | 05-17-2012 |
Patent application number | Description | Published |
20090236583 | Method of fabricating a phase change memory and phase change memory - The present invention relates to a phase change memory and a method of fabricating a phase change memory. The phase change memory includes a heater structure disposed on a phase change material pattern, wherein the heater structure is in a tapered shape with a bottom portion contacting the phase change material pattern. The fabrication of the phase change memory is compatible with the fabrication of logic devices, and accordingly an embedded phase change memory can be fabricated. | 09-24-2009 |
20100012916 | PHASE CHANGE MEMORY - A phase change memory and the method for manufacturing the same are disclosed. The phase change memory includes a word line, a phase change element, a plurality of heating parts, and a plurality of bit lines. The phase change material layer is electrically connected to the word line and the heating parts. Each heating part is electrically connected to a respective bit line. | 01-21-2010 |
20100133503 | PHASE CHANGE MEMORY - A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction. | 06-03-2010 |
20100133649 | Contact efuse structure, method of making a contact efuse device containing the same, and method of making a read only memory containing the same - A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse device or a read only memory. A method of making a contact efuse device and a method of making a read only memory are also disclosed. | 06-03-2010 |
20100148915 | ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME - An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element. | 06-17-2010 |
20110074538 | ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME - An electrical fuse structure is disclosed. The electrical fuse structure includes: a fuse element disposed on surface of a semiconductor substrate; an anode electrically connected to one end of the fuse element; and a cathode electrically connected to another end of the fuse element, wherein no silicide is formed on at least part of the cathode of the electrical fuse structure. | 03-31-2011 |
20110117710 | METHOD OF FABRICATING EFUSE, RESISTOR AND TRANSISTOR - A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess. | 05-19-2011 |
Patent application number | Description | Published |
20100282304 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - A bi-functional photovoltaic device is provided. The bi-functional photovoltaic device includes at least one solar cell and a control device. Each of the solar cell includes a multilayer semiconductor layer of group III-V compound semiconductor, a first electrode disposed on the back of the multilayer semiconductor layer, and a second electrode disposed on the front of the multilayer semiconductor layer. The control device connects with the at least one solar cell in order to control them functioning as solar cell or light emitting diode. | 11-11-2010 |
20110120527 | SOLAR ENERGY SYSTEM - The invention provides a solar energy system. A flexible transparent body includes a top surface, a bottom surface and two edges, wherein the top surface is a light receiving surface for receiving light with a first wave-length. A plurality of solar cells is disposed on at least one of the edges of the flexible transparent body, wherein the solar cells can covert light having a second wave-length into electrical energy. A wavelength converting layer is provided for converting light with the first wave-length to light with the second wave-length. | 05-26-2011 |
20110140540 | CHARGE APPARATUS - A charge apparatus including a natural energy conversion module, an energy converter, an energy transmitter, and an energy receiver is provided. The natural energy conversion module receives a natural energy and converts the natural energy into a first electric energy. The energy converter is electrically connected to the natural energy conversion module and converts the first electric energy into a wireless energy. The energy transmitter is electrically connected to the energy converter and transmits the wireless energy in a wireless manner. The energy receiver receives the wireless energy in a wireless manner and converts the wireless energy into a second electric energy. | 06-16-2011 |
20130170192 | DYE-LABELED POLYMER, SOLAR COLLECTOR AND METHODS FOR MANUFACTURING THE SAME, AND SOLAR CELL MODULE, AND OFF-GRID LAMP USING THE COLLECTOR - A dye-labeled polymer includes a fluorescent dye moiety and a polymer moiety, wherein the fluorescent dye moiety and the polymer moiety are connected through a chemical bond. | 07-04-2013 |
Patent application number | Description | Published |
20080270969 | METHOD FOR CORRECTING PHOTOMASK PATTERN - A method for correcting a photomask pattern is provided. The correcting method performs a verification of a focus-exposure matrix (FEM) and an overlay variation on a layout area having contact holes or vias in a layout pattern so as to generate a hint information. The layout pattern of the photomask is corrected according to the hint information to prevent the contact holes or vias from being exposed in arrangement to corresponding metal layer, poly layer, or diffusion layer. | 10-30-2008 |
20080295062 | Method of verifying a layout pattern - A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns. | 11-27-2008 |
20090300576 | METHOD FOR AMENDING LAYOUT PATTERNS - A method for amending layout patterns is disclosed. First, a layout pattern after an optical proximity correction is provided, which is called an amended pattern. Later, a positive sizing procedure and a negative sizing procedure are respectively performed on the amended pattern to respectively obtain a positive sizing pattern and a negative sizing pattern. Then, the positive sizing pattern and the negative sizing pattern are respectively verified to know whether they are useable. Afterwards, the useable positive sizing pattern and the negative sizing pattern are output for the manufacture of a reticle when they are verified to be useable. | 12-03-2009 |
20100036644 | METHOD FOR SELECTIVELY AMENDING LAYOUT PATTERNS - A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output. | 02-11-2010 |
20100070944 | METHOD FOR CONSTRUCTING OPC MODEL - A method for constructing an optical proximity correction (OPC) model is described. A test pattern is provided, and the test pattern is then written on a mask. The pattern on the mask is measured to obtain a modified pattern. An OPC model is constructed according to the modified pattern. | 03-18-2010 |
20100131914 | METHOD TO DETERMINE PROCESS WINDOW - A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output. | 05-27-2010 |
Patent application number | Description | Published |
20100182114 | METHOD FOR ADJUSTING INDUCTANCE OF CHOKE AND METHOD FOR DESIGNING CHOKE - A method for adjusting the inductance of a choke is provided by the present invention. The method includes with an unchanged structure and unchanged dimensions of the core of the choke, changing the kind of the magnetic materials composing the cores so as to adjust the magnetic permeability of the magnetic material. In addition, the present invention also provides a method for designing a choke, the method includes determining the structure of a first choke and a second choke, determining the dimensions of the cores of the chokes, and selecting magnetic materials composing the cores. | 07-22-2010 |
20100182115 | WIRE WOUND TYPE CHOKE COIL - A choke coil including a drum-core and at least one wire is provided. The drum-core includes a pillar, a first board and a second board. Two ends of the pillar are respectively connected to the first board and the second board. A material of the drum-core includes ferrous alloy. The wire has a winding portion wrapped around the pillar. | 07-22-2010 |
20100219924 | CHOKE - An electronic device including a core, at least a wire and a magnetic material is provided. The core includes a pillar, a top board and a bottom board. The pillar is disposed between the top board and the bottom board. An area of the top board is smaller than an area of the bottom board. A winding space is fanned among the top board, the bottom board and the pillar. The wire is winded around the pillar and located in the winding space. The magnetic material fills the winding space to encapsulate the wire. The magnetic material includes a resin and a metallic powder, wherein an average particle diameter of the magnetic powder is smaller than 20 μm. | 09-02-2010 |
20110048797 | SURFACE MOUNTED ELECTRONIC COMPONENT - A surface mounted electronic component is provided. The surface mounted electronic component includes a main body, a circuit element, a conductive electrode, and a virtual electrode. The circuit element is arranged in the main body. The conductive electrode is disposed on an outer surface of the main body, wherein the conductive electrode electrically is connected to the circuit element. The virtual electrode is disposed on the outer surface of the main body, wherein the virtual electrode lies near the conductive electrode. There is a distance between the virtual electrode and the conductive electrode. | 03-03-2011 |
20150055315 | Electronic package structure and method for making the same - An inductive component is disclosed. The inductive component comprises a magnetic body and a coil in the magnetic body, wherein a first protrusion and a second protrusion are formed on the bottom surface of the magnetic body, wherein the first protrusion comprises a first electrode disposed on the peak surface of the first protrusion, and the second protrusion comprises a second electrode disposed on the peak surface of the second protrusion, wherein the first electrode and the second electrode are electrically connected to a first end and a second end of the coil, and a space is formed by the first protrusion, the second protrusion and the bottom surface of the magnetic body for accommodating electronic devices. | 02-26-2015 |
Patent application number | Description | Published |
20080266531 | DISPLAY APPARATUS, ELECTRONIC APPARATUS, AND REFLECTIVE MIRROR MODULE - A display apparatus including a main body and a housing is provided. The main body includes a light source and a light modulator module. The light source is used for providing a beam. The light modulator module modulates the beam according to an electrical image signal. The housing includes a base, an upper cover, and a reflective mirror. The base has an opening for allowing the modulated beam to pass through. The upper cover is pivotally connected to the base. The reflective mirror is disposed on the upper cover. The modulated beam passing through the opening is suitable to be reflected by the reflective mirror. An electronic apparatus and a reflective mirror module are also provided. | 10-30-2008 |
20100039603 | DISPLAY PANEL MODULE - An LCOS panel module including a substrate, a flexible printed circuit (FPC), an LCOS panel, and a face mask is provided. The substrate has an adhesive region on a surface thereof The FPC is disposed on the substrate and has an opening for exposing the adhesive region. The LCOS panel has a bottom surface and a top surface. The bottom surface of the LCOS panel is fixed on the adhesive region of the substrate exposed from the opening through an adhesive layer and is electrically connected to the FPC. The face mask used for framing the display region of the LCOS panel and sheltering from stray light is disposed on the LCOS panel and has a display opening. A display region of the top surface of the LCOS panel is exposed from the display opening of the face mask. | 02-18-2010 |
20100238672 | LIGHT-EMITTING DIODE LIGHT BULB AND APPLICATION THEREOF - A light-emitting diode (LED) light bulb and an application thereof are described. The light-emitting diode light bulb comprises: a light-emitting diode light source module; a base, wherein the light-emitting diode light source module is disposed on the base; and a driver portion to drive the light-emitting diode light source module, comprising a rotation shaft, wherein the driver portion is connected to the base via the rotation shaft, such that the light-emitting diode light source module can rotate relative to the driver portion. | 09-23-2010 |