Wu, Nantou County
Chien-Han Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20160064974 | BATTERY PROTECTION INTEGRATED CIRCUIT APPLIED TO BATTERY CHARGING/DISCHARGING SYSTEM AND METHOD FOR DETERMINING RESISTANCES OF VOLTAGE DIVIDER OF BATTERY PROTECTION INTEGRATED CIRCUIT - A battery protection IC applied to a battery charging system is provided, where the battery charging system includes a charger and a switch, the switch is coupled between the charger and a battery when the battery is put into the battery charging system, and the battery protection IC includes a voltage divider, a comparator and a controller. The voltage divider is coupled to a first node of the switch, and is utilized for dividing a voltage of the first node to generate a divided voltage, whereat least one resistor of the voltage divider is formed by two different types of fuses. The comparator is utilized for comparing the voltage with a reference voltage to generate a comparison result. The controller is utilized for generating a control signal according to the comparison result, where the control signal is utilized for switching on or switching off the switch. | 03-03-2016 |
Chien-Nan Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20110072123 | AUTO-METER SYSTEM WITH CONTROLLER AREA NETWORK BUS - An auto-meter system includes a CAN-Bus for transmitting a CAN-Bus signal, and a first CAN module coupled to the CAN-Bus. The first CAN module is for receiving the CAN-Bus signal transmitted from the CAN-Bus and for transforming the CAN-Bus signal to a message signal. The auto-meter system further includes a display and a processor coupled to the CAN module and the display. The processor is for receiving the message signal and for controlling the display to show information corresponding to the message signal. | 03-24-2011 |
Ching-Wei Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20140112048 | N-BIT ROM CELL - Among other things, an n-bit ROM cell, such as a twin-bit ROM cell, and techniques for addressing one or more ROM cell portions of the n-bit ROM cell are provided. A twin-bit ROM cell comprises a first ROM cell portion adjacent to or substantially contiguous with a second ROM cell portion. The first ROM cell portion is associated with a first data bit value. The second ROM cell portion is associated with a second data bit value distinct from the first data bit value. Because the first ROM cell portion is adjacent to the second ROM cell portion, OD-to-OD spacing between the twin-bit ROM cell and an adjacent twin-bit ROM cell is increased to provide, for example, improved isolation, cell current, ROM speed, and VCCmin performance in comparison with single-bit ROM cells, while maintaining a substantially similar to pitch as the single-bit ROM cells. | 04-24-2014 |
20140146631 | VCCMIN FOR A DUAL PORT SYNCHRONOUS RANDOM ACCESS MEMORY (DPSRAM) CELL UTILIZED AS A SINGLE PORT SYNCHRONOUS RANDOM ACCESS MEMORY (SPSRAM) CELL - One or more techniques for improving Vccmin for a dual port synchronous random access memory (DPSRAM) cell utilized as a single port synchronous random access memory (SPSRAM) cell are provided herein. In some embodiments, a second word line signal is sent to a second word line of the DPSRAM cell. For example, the second word line signal is sent in response to a logical low at a first bit line or a logical low at a second bit line. In this way, Vccmin is improved for the DPSRAM cell. | 05-29-2014 |
20150248928 | BOOST SYSTEM FOR DUAL-PORT SRAM - A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal. | 09-03-2015 |
Chung-Hao Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20130308698 | RATE AND DISTORTION ESTIMATION METHODS AND APPARATUS FOR COARSE GRAIN SCALABILITY IN SCALABLE VIDEO CODING - Mode-dependent rate and distortion estimation methods for coarse grain scalability (CGS) in scalable video coding (SVC) are provided. The rate and distortion values of a base layer and an enhancement layer are estimated based on different combinations of a block partition size of the base layer block, a transform block size of the base layer transform, and a quantization parameter of the base layer quantization as well as a block partition size of the enhancement layer block, a transform block size of the enhancement layer transform, a quantization parameter of the enhancement layer, and a setting of the inter-prediction, and a mode pair for CGS in SVC may be selected accordingly based on the estimation of the rate and distortion values of the base layer and the enhancement layer. The disclosure also provides a mode-dependent rate and distortion estimation apparatus to realize the above method. | 11-21-2013 |
Chun-Ming Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20090120785 | METHOD FOR FORMING METAL FILM OR STACKED LAYER INCLUDING METAL FILM WITH REDUCED SURFACE ROUGHNESS - A method for forming a stacked layer with a reduced surface roughness that includes at least a metal film and an anti-reflection coating thereon is described. A sputtering process is conducted using a metal target to deposit a layer of metal on a substrate, wherein the DC power density over the sputtered surface of the metal target is set higher than 5 W/inch | 05-14-2009 |
Chun-Pei Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20100006974 | STORAGE NITRIDE ENCAPSULATION FOR NON-PLANAR SONOS NAND FLASH CHARGE RETENTION - The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings. | 01-14-2010 |
Feng-Chi Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20090290562 | METHOD OF DELIVERING MULTICAST PACKETS IN A MESH NETWORK - In a mesh network, when a wireless mesh link exists between a first mesh access point and a second mesh access point, the first mesh access point can deliver a multicast packet to the second mesh access point through the wireless mesh link. When the second mesh access point determines that the multicast packet from the first mesh access point is a redundant packet, the second mesh access point will send a multi-path notice to the first mesh access point. After receiving the multi-path notice, the first mesh access point stops delivering the multicast packet through the path. | 11-26-2009 |
20100329168 | Frequency Band Assignment Method for a Wireless Communication System and Device Using the Same - A frequency band assignment method for a wireless communication system is disclosed. The wireless communication system includes a plurality of base stations. The plurality of base stations has overlapped radio ranges and forms a plurality of independent overlapping areas. The method includes steps of modeling the plurality of base stations as a plurality of variable nodes in a factor graph, modeling the plurality of independent overlapping areas as a plurality of constraint nodes in the factor graph, and using the factor graph to perform frequency assignment for the plurality of base stations. Each variable node is defined as a frequency band to be assigned to the modeled base station. Each constraint node is defined as that the frequency bands assigned to the base stations forming the modeled overlapping area cannot be equivalent. | 12-30-2010 |
20110007722 | Base Station Selection Method for a Wireless Communication System and Device Using the Same - A base station selection method is disclosed. The wireless communication system includes a plurality of base stations with overlapped radio ranges and a plurality of wireless devices. The method includes steps of modeling the plurality of base stations as a plurality of variable nodes in a factor graph, modeling the plurality of wireless devices as a plurality of constraint nodes in the factor graph, and selecting a base station for transmission from the plurality of base stations based on the factor graph. Each variable node is defined as a frequency band state of a corresponding base station. Each constraint node is linked to the variable nodes corresponding to the base stations that include the corresponding wireless device in their radio ranges, and is defined as that the frequency band states of the base stations including the corresponding wireless device in their radio ranges can not be all turned off. | 01-13-2011 |
Gwo-Tswin Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20100102917 | INDUCTOR - An inductor includes a first core, a second core, a protruding structure, at least two gaps and a conducting wire. The first core has a protruding portion. The second core is disposed opposite to the first core. The protruding structure protrudes from the protruding portion of the first core and toward the second core. The at least two gaps are between the protruding portion of the first core and the second core. The conducting wire winds around at least one of the first and second cores. The conducting wire has a specific resistance value of 1.42 μΩm or lower. | 04-29-2010 |
Hsin-Hung Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20140361610 | VOLTAGE REGULATOR, OPERATION METHOD THEREOF, VOLTAGE REGULATING SYSTEM, AND MOBILE VEHICLE - A voltage regulator, an operation method thereof, and a voltage regulating system, and a mobile vehicle are provided. The voltage regulator coupled to an alternator and a battery includes a voltage detection unit which is coupled to the alternator and a startup assisting unit. The voltage detection unit operatively generates an enable signal responsive to an output voltage of the alternator. The startup assisting unit is coupled to the alternator, the battery, and the voltage detection unit. The startup assisting unit operatively generates a first exciting current to excite a rotor coil according to the enable signal. When the voltage detection unit detects that the output voltage is greater than a predetermined voltage threshold, the voltage detection unit outputs the enable signal causing the startup assisting unit to generate the first exciting current to the rotor coil, thereby facilitating the alternator to establish voltage under low rotational speed. | 12-11-2014 |
Kun-Ta Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20140024944 | FLOW VELOCITY ESTIMATION AND ULTRASOUND SYSTEMS FOR FLOW VELOCITY ESTIMATION - Systems and methods for measuring flow velocities, including ultrasound systems, are provided. A Doppler angle between a direction of ultrasound signals and an axis of a flow may be estimated to improve the accuracy of the flow velocity estimation that is based on Doppler effects. A sensor may be mounted on or in an ultrasound probe to obtain a reference orientation of the ultrasound probe and an orientation of the ultrasound probe relative to the reference orientation when the ultrasound probe is moved to other positions. The Doppler angle may be estimated based on the orientation of the ultrasound probe. | 01-23-2014 |
Ming-Chou Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20130250072 | 2D/3D DISPLAY AND METHOD FOR FORMING 3D IMAGE - A display capable of providing 2D and/or 3D images. The display comprises a liquid crystal display device and a self-emissive display device. The self-emissive display device is disposed on the rear of the liquid crystal display device, in which the liquid crystal display device provides a first image and the self-emissive display device a second image and a backlight source. One of the first and second images comprises a parallax barrier pattern for forming a three-dimensional (3D) image, and the other is a 2D image. | 09-26-2013 |
Min-Hong Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20090187866 | Electrical Parameter Extraction for Integrated Circuit Design - A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver. | 07-23-2009 |
20090222785 | METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION - An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout. | 09-03-2009 |
20100095253 | TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 04-15-2010 |
20110289466 | Table-Based DFM for Accurate Post-Layout Analysis - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 11-24-2011 |
Sin-Huei Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20150091952 | SUB-PIXEL DRIVING SYSTEM AND THE DRIVING METHOD THEREOF - An exemplary embodiment provides a sub-pixel driving system including a display panel, an image receiver, a control unit, an image-arrangement unit, and a driving unit. The display panel includes a plurality of pixels having a plurality of sub-pixels, wherein the display panel has a display characteristic. The image receiver receives a plurality of sub-pixel gradation signals. The control unit provides at least one driving parameter and determines a predetermined driving order, both according to the display characteristic. The image-arrangement unit arranges the sub-pixel gradation signals in a specific order according to the driving parameter. The driving unit drives the sub-pixels by the sub-pixel gradation signals that are arranged in the specific order according to the predetermined driving order. | 04-02-2015 |
Tsung-Ming Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20150270600 | PERSONAL ELECTRONIC DEVICE - A personal electronic device has its modules wirelessly connected for communications between the modules. The personal electronic device comprises a frame module, a peripheral module, a battery unit, and a plurality of power lines. The frame module and the peripheral module are each equipped with a wireless chipset and an antenna. The communication between the frame module and the peripheral module is accomplished only through wireless signals. There are no wires and sockets for connecting the frame module to the peripheral module. Costs related to wires and sockets manufacture and installation are thereby reduced. | 09-24-2015 |
Yu-Hsiao Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20080272996 | DISPLAY SYSTEM AND COMPENSATION CIRCUIT THEREOF - A display system comprises an adjustment unit, a pulse generating unit and a light tube. The adjustment unit comprises a thermal resistor and generates an adjustment signal according to the temperature. The pulse generating unit generates a pulse driving signal according to the adjusting signal. When the temperature falls, the duty cycle of the pulse driving signal is increased. When the temperature rises, the duty cycle of the pulse driving signal is decreased. The light tube emits light according to the duty cycle of the pulse driving signal. | 11-06-2008 |
Yu-Zhi Wu, Nantou County TW
Patent application number | Description | Published |
---|---|---|
20110304805 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel includes an active device array substrate, an opposite substrate, a sealant, a liquid crystal layer, a black matrix, and a plurality of rough structures. The active device array substrate has a display area and a peripheral area surrounding the display area, and the liquid crystal layer and the peripheral area are surrounded by the sealant. The black matrix is disposed between the active device array substrate and the opposite substrate and distributed corresponding to the display area and the peripheral area. The rough structures are disposed on a portion of the black matrix and distributed corresponding to the peripheral area. Surface roughness of the rough structures is greater than surface roughness of the black matrix distributed corresponding to the display area. | 12-15-2011 |
20120033114 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, multiple scan lines, multiple data lines, multiple of pixels are provided. The scan lines and the data lines are disposed on the substrate. Each pixel includes multiple sub-pixels including at least a transistor, a pixel electrode, and a color filter. The transistor is disposed on the substrate and electrically connected to the scan line and the data line correspondingly. A portion of the color filter is disposed between the pixel electrode and the corresponding scan line. The pixel electrode is coupled with the corresponding scan line to form a first capacitor. The drain of the transistor is coupled with the corresponding scan line to form a second capacitor. In a single pixel, the coupling areas of the pixel electrodes corresponding to various color filters with the corresponding scan lines are different, so that capacitance of the first capacitors are substantially the same. | 02-09-2012 |
20140071385 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel includes an active device array substrate, an opposite substrate, a sealant, a liquid crystal layer, a black matrix, and a plurality of rough structures. The active device array substrate has a display area and a peripheral area surrounding the display area, and the liquid crystal layer and the peripheral area are surrounded by the sealant. The black matrix is disposed between the active device array substrate and the opposite substrate and distributed corresponding to the display area and the peripheral area. The rough structures are disposed on a portion of the black matrix and distributed corresponding to the peripheral area. Surface roughness of the rough structures is greater than surface roughness of the black matrix distributed corresponding to the display area. | 03-13-2014 |