Wu, Cupertino
Arthur Chao-Chung Wu, Cupertino, CA US
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20120120016 | IMAGE OF A KEYBOARD - A system or method including a display and sensor to detect touches of the display. The display can display an image of a keyboard. The image of the keyboard can be shaped to the locations of the touches of the display. | 05-17-2012 |
Biao Wu, Cupertino, CA US
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20160035600 | METHODS AND APPARATUSES FOR DEUTERIUM RECOVERY - Novel methods, systems, and apparatuses for reclaiming annealing gases from a high pressure annealing processing system are disclosed. According to an embodiment, the exhaust gasses from the high pressure annealing processing system are directed into a gas reclaiming system only when a precious gas, e.g., deuterium is used. The annealing gas is the separated from other gasses used in the high pressure annealing processing system and is then pressurized, filtered, and purified prior to transferring the gas to a bulk storage distribution unit. In one embodiment, the reclaimed gas is then again provided to the high pressure annealing processing system to anneal the wafers. | 02-04-2016 |
Bridget Bin Wu, Cupertino, CA US
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20110301885 | SYSTEM AND METHOD FOR TESTING A LIGHT SENSOR OF A PORTABLE ELECTRONIC DEVICE - An improved system and method for testing a sensor of a portable electronic device based on expected sensor data and not timing information. The system and method for testing a sensor of a portable electronic device retrieves sensed data from the portable electronic device (i.e. device under test) after the device has traversed a series of test areas or zones. The sensed data is compared against a set of expected sensor data patterns to determine which components of the sensed data correspond to each test area or zone. The sensor of the portable electronic device may be tested based on an association of the test areas or zones with segments of the sensed data. | 12-08-2011 |
Chang-Hong Wu, Cupertino, CA US
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20100177777 | PRESERVING THE ORDER OF PACKETS THROUGH A DEVICE - A network device includes one or more sprayers, multiple packet processors, and one or more desprayers. The sprayers receive packets on at least one incoming packet stream and distribute the packets according to a load balancing scheme that balances the number of bytes of packet data that is given to each of the packet processors. The packet processors receive the packets from the sprayers and process the packets to determine routing information for the packets. The desprayers receive the processed packets from the packet processors and transmit the packets on at least one outgoing packet stream based on the routing information. | 07-15-2010 |
20110235642 | PRESERVING THE ORDER OF PACKETS THROUGH A DEVICE - A network device includes one or more sprayers, multiple packet processors, and one or more desprayers. The sprayers receive packets on at least one incoming packet stream and distribute the packets according to a load balancing scheme that balances the number of bytes of packet data that is given to each of the packet processors. The packet processors receive the packets from the sprayers and process the packets to determine routing information for the packets. The desprayers receive the processed packets from the packet processors and transmit the packets on at least one outgoing packet stream based on the routing information. | 09-29-2011 |
Changxun Wu, Cupertino, CA US
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20150287047 | Extracting Information from Chain-Store Websites - Provided is a process of extracting structured chain-store data from chain-store websites, the process including: identifying, via a processor, a store-locator webpage from a store website; querying the store-locator webpage for store locations in a geographic area; detecting a repeating pattern in a document object model (DOM) of a responsive webpage returned by the store website, the repeating pattern containing location information for stores in the geographic area; extracting, from the repeating pattern, location information for the stores in the geographic area; and storing the location information in a business listing repository. | 10-08-2015 |
Chien-Hsien Wu, Cupertino, CA US
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20090086634 | METHOD AND SYSTEM FOR PACKET RATE SHAPING - Aspects of a method and system for packet rate shaping may include an MMU that enables classification of one or more packets based on a CoS and/or an egress port, and transmission of the packets in accordance with a specified packet rate based on the classification. | 04-02-2009 |
20090168777 | COMPRESSION OF DATAGRAM DISTRIBUTION INFORMATION - A first set of instructions associated with an egress of a datagram may be determined, the first set of instructions identifying a first subset of a second set of instructions, the first subset including multiple individual network identifiers identifying which network portion to transmit a replication of the datagram. Which one of the multiple individual network identifiers corresponds to the datagram may be determined from the first subset of the second set of instructions and may be based on the egress of the datagram, wherein each network identifier corresponds to a different egress. The replication of the datagram may be provided to the egress of the determined network identifier for transmission to the network portion as identified by the determined network identifier corresponding to the datagram. | 07-02-2009 |
20110194450 | CELL COPY COUNT HAZARD DETECTION - The present invention is directed to a network device, method and apparatus for processing data. The present invention includes at least one ingress module for performing switching functions on incoming data. The invention further includes a memory management unit (MMU) for storing the incoming data, and at least one egress module for transmitting the incoming data to at least one egress port. Further, in the present invention, the memory management unit further comprises a cell copy count pool (CCP) memory, wherein the CCP determines when a memory cell can be made available. | 08-11-2011 |
20140044128 | SERIAL REPLICATION OF MULTICAST PACKETS - Disclosed are various embodiments that provide serial replication of multicast packets by performing a first data fetch to fetch first data from a memory buffer, the first data comprising a first packet pointer representing a first packet and a replication number indication a number of times the first packet is to be replicated. Furthermore, various embodiments are directed to performing a second data fetch to fetch second data from a memory buffer, the second data comprising a first packet pointer representing a second packet and serially replicating the first packet and the second packet based at least in part upon the replication number and a predetermined threshold value. | 02-13-2014 |
20140052912 | MEMORY DEVICE WITH A LOGICAL-TO-PHYSICAL BANK MAPPING CACHE - A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank. | 02-20-2014 |
20140052913 | MULTI-PORTED MEMORY WITH MULTIPLE ACCESS SUPPORT - A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation. | 02-20-2014 |
20140052914 | MULTI-PORTED MEMORY WITH MULTIPLE ACCESS SUPPORT - A multi-ported memory that supports multiple read and write accesses is described. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for read operation(s) and write operation(s) to be received during the same clock cycle. In the event that an incoming write operation is blocked by read operation(s), data for that write operation may be stored in one of a plurality of cache banks included in the multi-port memory. The cache banks are accessible to both write and read operations. In the event than the write operation is not blocked by read operation(s), a determination is made as to whether data for that incoming write operation is stored in the memory bank targeted by that incoming write operation or in one of the cache banks. | 02-20-2014 |
Frederick C. Wu, Cupertino, CA US
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20080227291 | FORMATION OF COMPOSITE TUNGSTEN FILMS - Embodiments of the invention provide methods for depositing tungsten materials. In one embodiment, a method for forming a composite tungsten film is provided which includes positioning a substrate within a process chamber, forming a tungsten nucleation layer on the substrate by subsequently exposing the substrate to a tungsten precursor and a reducing gas containing hydrogen during a cyclic deposition process, and forming a tungsten bulk layer during a plasma-enhanced chemical vapor deposition (PE-CVD) process. The PE-CVD process includes exposing the substrate to a deposition gas containing the tungsten precursor while depositing the tungsten bulk layer over the tungsten nucleation layer. In some example, the tungsten nucleation layer has a thickness of less than about 100 Å, such as about 15 Å. In other examples, a carrier gas containing hydrogen is constantly flowed into the process chamber during the cyclic deposition process. | 09-18-2008 |
20080268171 | APPARATUS AND PROCESS FOR PLASMA-ENHANCED ATOMIC LAYER DEPOSITION - Embodiments of the invention provide an apparatus configured to form a material during an atomic layer deposition (ALD) process, such as a plasma-enhanced ALD (PE-ALD) process. In one embodiment, a plasma baffle assembly for receiving a process gas within a plasma-enhanced vapor deposition chamber is provided which includes a plasma baffle plate containing an upper surface to receive a process gas and a lower surface to emit the process gas, a plurality of openings configured to flow the process gas from above the upper surface to below the lower surface, wherein each opening is positioned at a predetermined angle of a vertical axis that is perpendicular to the lower surface, and a conical nose cone on the upper surface. In one example, the openings are slots positioned at a predetermined angle to emit the process gas with a circular flow pattern. | 10-30-2008 |
20120315756 | PROCESS FOR ELECTROLESS COPPER DEPOSITION ON A RUTHENIUM SEED - Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide. | 12-13-2012 |
Heng-Hsi Wu, Cupertino, CA US
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20140069567 | T-FLEX BONDER - A flexible circuit with multiple independent mounting points can be mounted (soldered) to substrates by independently (and concurrently) positioning mounting points in x, y, and theta (angular rotation) with vacuum chucks. In one embodiment the vacuum chucks can be guided by computer aided vision to locate and match fiducials on the flex circuit with fiducials on the substrate. In one embodiment, hot bars can be used in a subsequent bonding operation to secure an adhesive coupling between the flexible circuits and the substrate. | 03-13-2014 |
Hui-Chin Wu, Cupertino, CA US
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20100166431 | OPTICAL TRANSCEIVER IC - A power management arrangement for low power optical transceiver such as those that may be integrated into a personal computer or server may periodically put itself into a power conservation or sleep mode which assures the transceiver is available upon wake-up. | 07-01-2010 |
20110222860 | METHOD AND APPARATUS FOR GENERATING A REFERENCE SIGNAL LEVEL AND FOR CANCELLING AMPLIFIER OFFSET IN AN OPTICAL SYSTEM - Described is a method and apparatus for generating a mid-level reference signal and for cancelling amplifier offset in an optical communication system without DC-balancing of optical data. The apparatus comprises an optical-to-electrical converter to receive an optical signal and to generate an electrical signal; an amplifier to receive the electrical signal and to generate an output signal based on a reference signal; a feedback mechanism to be enabled during a training phase only and to generate a control signal from the output signal; and a counter logic having a digital-to-analog converter to generate the reference signal based on the control signal. | 09-15-2011 |
20120170941 | OPTICAL TRANSCEIVER IC - A power management arrangement for low power optical transceiver such as those that may be integrated into a personal computer or server may periodically put itself into a power conservation or sleep mode which assures the transceiver is available upon wake-up. | 07-05-2012 |
20140093233 | OPTICAL LINK AUTO-SETTING - A system includes two optical modules that perform auto-setting of the optical links between the optical modules. One optical module sends an optical signal with a test pattern to the other optical module. If the receiving module determines that the test pattern is successfully received, it sends a pass indication to the transmitting module, and the transmitting module can configure its driver path in accordance with a transmit current setting used to transmit the test pattern. If the test pattern is not successfully received, the receiving module sends a fail indication, and the transmitting module can increase the transmit current setting and resend the test pattern. When the system includes multiple optical channels, one channel can be tested while feedback is provided on another channel. The system can iterate through all optical channels until they are all configured. | 04-03-2014 |
20140133846 | OPTICAL LINK HANDSHAKE TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure provide optical link handshake techniques and configurations. In one embodiment, an optical module includes a laser driver corresponding with a channel of the optical module, a signal detector corresponding with the channel, and a link handshake state machine configured to control the laser driver to generate a connect pulse of a link handshake process to test an optical link between the channel and a corresponding channel of another optical module and monitor the signal detector to detect a connect pulse from the another optical module. Other embodiments may be described and/or claimed. | 05-15-2014 |
20140186046 | LASER SAFETY TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure provide laser safety techniques and configurations. In one embodiment, an optical module includes a first die including a laser configured to transmit optical signals, a first node electrically coupled with the laser, and a second node electrically coupled with the laser, and a second die including a power supply line configured to provide power to the laser, a third node electrically coupled with the power supply line and electrically coupled with the first node to provide the power to the laser, a fourth node electrically coupled with the second node of the first die, and a switch configured to prevent the power of the power supply line from reaching the laser through the third node based on a voltage of the fourth node when a laser fault event occurs. Other embodiments may be described and/or claimed. | 07-03-2014 |
Hung Jen (henry) Wu, Cupertino, CA US
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20080279310 | ENHANCED SIGNALING SENSITIVITY USING MULTIPLE REFERENCES - A receiver circuit uses two or more comparators to detect the received data signal. Each comparator is set to compare the data signal to a different reference signal. The output signals of the comparators are received into a detector circuit, which provides a third output signal that establishes the logic state of the received signal based on whether or not the output signals of the comparators are equal. Depending on the logic state of the data signal, one of the comparators provides its output signal sooner than the other. Each comparator may be implemented by a differential amplifier. In one embodiment, the reference signals are threshold voltages which may be provided by the tripping voltages at the trip points for the logic HIGH and LOW states. | 11-13-2008 |
Kuang Jen J. Wu, Cupertino, CA US
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20080210857 | Imaging mass spectrometer with mass tags - A method of analyzing biological material by exposing the biological material to a recognition element, that is coupled to a mass tag element, directing an ion beam of a mass spectrometer to the biological material, interrogating at least one region of interest area from the biological material and producing data, and distributing the data in plots. | 09-04-2008 |
20110147589 | ROOM TEMPERATURE ALUMINUM ANTIMONIDE RADIATION DETECTOR AND METHODS THEREOF - In one embodiment, a method for producing a high-purity single crystal of aluminum antimonide (AlSb) includes providing a growing environment with which to grow a crystal, growing a single crystal of AlSb in the growing environment which comprises hydrogen (H | 06-23-2011 |
20120161288 | THERMAL OXIDATION OF SINGLE CRYSTAL ALUMINUM ANTIMONIDE AND MATERIALS HAVING THE SAME - In one embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a partial vacuum atmosphere at a temperature conducive for air adsorbed molecules to desorb, surface molecule groups to decompose, and elemental Sb to evaporate from a surface of the AlSb crystal and exposing the AlSb crystal to an atmosphere comprising oxygen to form a crystalline oxide layer on the surface of the AlSb crystal. In another embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a non-oxidizing atmosphere at a temperature conducive for decomposition of an amorphous oxidized surface layer and evaporation of elemental Sb from the AlSb crystal surface and forming stable oxides of Al and Sb from residual surface oxygen to form a crystalline oxide layer on the surface of the AlSb crystal. | 06-28-2012 |
Kung Chris Wu, Cupertino, CA US
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20130043776 | OPENER FOR EXTREME ULTRA VIOLET LITHOGRAPHY RETICLE PODS - A two stage opener ( | 02-21-2013 |
20130108409 | THIN SUBSTRATE, MASS-TRANSFER BERNOULLI END-EFFECTOR | 05-02-2013 |
Peter Wu, Cupertino, CA US
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20120131326 | SECURING PARTNER-ENABLED WEB SERVICE - The claimed subject matter provides a method for securing a partner-enabled web service. The method includes receiving a request to access the partner-enabled web service. The request is received from a browser client for a partner application. The browser client is associated with a user. Additionally, the method includes determining that the user is authorized to access the partner application. The method further includes generating a token that associates the user with the partner application. Also, the method includes sending the token to the browser client. | 05-24-2012 |
20130036460 | Cross-domain Session Refresh - Various embodiments utilize redirection techniques to refresh an authenticated session for a web-based executable operated across multiple domains. In at least some embodiments, the redirection techniques utilize a hidden inline frame (“i-frame”) to refresh an authenticated session. In some embodiments, polling is utilized to detect the end of a redirection sequence and a refreshed authenticated session while in other embodiments, an authenticated session is assumed to be refreshed after the expiration of a predetermined period of time. | 02-07-2013 |
20150365419 | SECURING PARTNER-ENABLED WEB SERVICE - The claimed subject matter provides a method for securing a partner service. The method can include receiving a request, wherein the request comprises a unique value, to access the partner service, wherein the request is received from a browser client for a partner application and determining that a user is authorized to access the partner application, the partner application generating a token that associates the user with the partner application. The method can also include generating a signature for the token, the signature to enable the partner service to independently regenerate the signature, the token comprising an identifier for the partner application enabling the partner service to detect which partner application generates the token and sending the token with the signature to the browser client. | 12-17-2015 |
Peter Gene Wu, Cupertino, CA US
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20150242080 | Propagating Theming Information from Host Applications to Host Extensions - Mechanisms are described herein for propagating a theme definition from a host application to a host extension so that the host application and the host extension are visually consistent. A theme definition may be updated after a theme change event occurs as a result of a user interacting with the host application. The theme definition may then be utilized by the host extension to update one or more UI elements presented by the host extension to enable visual consistency. | 08-27-2015 |
Ping-Chih Wu, Cupertino, CA US
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20100122228 | METHOD AND SYSTEM FOR CONDUCTING DESIGN EXPLORATIONS OF AN INTEGRATED CIRCUIT - Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations. | 05-13-2010 |
Raymond Wu, Cupertino, CA US
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20080225160 | Mobile Devices Having An Image Sensor For Charging A Battery - Mobile devices and methods of operating mobile devices are disclosed herein. In one embodiment, a mobile device includes a rechargeable battery, a battery charger electrically coupled to the battery, and an image sensor operably coupled to the battery charger to selectively charge the battery. As such, the image sensor is configured to capture images and provide current to charge the battery. The image sensor can be a CMOS image sensor or a CCD image sensor. The mobile device may further include a housing, with the battery, battery charger, and image sensor contained within the housing. | 09-18-2008 |
Shao-Yong Wu, Cupertino, CA US
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20090318484 | Inhibitors of JNK - The invention relates to prodrugs of JNK inhibitors and corresponding methods, formulations, and compositions for inhibiting JNK and treating JNK-mediated disorders. The application discloses prodrugs of JNK inhibitors, as described below in formula I: | 12-24-2009 |
20110319656 | PROCESS FOR SYNTHESIS OF TRITIATED AND DEUTERATED THIORPHAN AND ACETORPHAN - Methods for preparing tritium or deuterium labeled thiorphan comprising reacting a compound of formula i | 12-29-2011 |
Shiquan Wu, Cupertino, CA US
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20140376601 | Adaptive Time Diversity And Spatial Diversity For OFDM - An adaptable orthogonal frequency-division multiplexing system (OFDM) that uses a multiple input multiple output (MIMO) to having OFDM signals transmitted either in accordance with time diversity to reducing signal fading or in accordance with spatial diversity to increase the data rate. Sub-carriers are classified for spatial diversity transmission or for time diversity transmission based on the result of a comparison between threshold values and at least one of three criteria. The criteria includes a calculation of a smallest eigen value of a frequency channel response matrix and a smallest element of a diagonal of the matrix and a ratio of the largest and smallest eigen values of the matrix. | 12-25-2014 |
Shun Wu, Cupertino, CA US
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20120107520 | Removing Residues from Substrate Processing Components - Residues are removed from a surface of a substrate processing component which has a polymer coating below the residues. In one version, the component surfaces are contacted with an organic solvent to remove the residues without damaging or removing the polymer coating. The residues can be process residues or adhesive residues. The cleaning process can be conducted as part of a refurbishment process. In another version, the residues are ablated by scanning a laser across the component surface. In yet another version, the residues are vaporized by scanning a plasma cutter across the surface of the component. | 05-03-2012 |
20140076354 | REMOVING RESIDUES FROM SUBSTRATE PROCESSING COMPONENTS - Residues are removed from a surface of a substrate processing component which has a polymer coating below the residues. In one version, the component surfaces are contacted with an organic solvent to remove the residues without damaging or removing the polymer coating. The residues can be process residues or adhesive residues. The cleaning process can be conducted as part of a refurbishment process. In another version, the residues are ablated by scanning a laser across the component surface. In yet another version, the residues are vaporized by scanning a plasma cutter across the surface of the component. | 03-20-2014 |
Shun Jackson Wu, Cupertino, CA US
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20080213496 | Method of coating semiconductor processing apparatus with protective yttrium-containing coatings - Methods of applying specialty ceramic materials to semiconductor processing apparatus, where the specialty ceramic materials are resistant to halogen-comprising plasmas. The specialty ceramic materials contain at least one yttrium oxide-comprising solid solution. Some embodiments of the specialty ceramic materials have been modified to provide a resistivity which reduces the possibility of arcing within a semiconductor processing chamber. | 09-04-2008 |
20080236620 | Methodology for cleaning of surface metal contamination from electrode assemblies - Systematic and effective methodology to clean capacitively coupled plasma reactor electrodes and reduce surface roughness so that the cleaned electrodes meet surface contamination specifications and manufacturing yields are enhanced. Pre-cleaning of tools used in the cleaning process helps prevent contamination of the electrode being cleaned. | 10-02-2008 |
Vickie Wu, Cupertino, CA US
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20130235239 | POWER SAVING TECHNIQUES FOR IMAGE SENSORS - Power saving techniques are provided for processing circuitry on image sensors. Processing circuitry may include one or more processing blocks. The processing blocks may receive pixel data in the form of lines separated by blanking time. To reduce power consumption, each processing block may have a clock that is enabled when processing data and disabled during blanking time. The processing blocks may have respective clocks that are enabled and disabled at different times. Timing control circuitry may provide a clock enable signal to a first processing block. Each processing block may receive a clock enable signal and output a time-shifted clock enable signal for a subsequent processing block. | 09-12-2013 |
Victor Chuan-Chen Wu, Cupertino, CA US
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20080218959 | Combo internal and external storage system - A combo internal and external storage system which comprising: an enclosure portion, having a plurality of openings on it's real wall and a hollow space for containing the storage device which further comprises a first power interface and a first data interface; and a first PCB, being disposed in the hollow space and further comprising a first connector, a second power interface, a second data interface, a second connector and a power connector; wherein the first connector is used to connect to the first power interface and first data interface of the storage device, the second data interface and second data interface are used to connect to a power interface and data interface of the cradle portion, and the second connector and power connector are used to connect to the computer or equipment by the cable. | 09-11-2008 |
20100205454 | CIPHER DATA BOX - A cipher data box comprises: a housing; a printed circuit board; a first connector; a second connector; a controller, having a unique first identification code; a key seat; and a key, having a unique second identification code; therefore, when the key is inserted into the key seat and the first identification code is same as the second identification code, the storage device can be normally accessed, and the data therein will be encrypted/decrypted. Furthermore, for further enhancing the security function of the storage device, a plurality of cipher data boxes of the present invention can be cascade each other. | 08-12-2010 |
Wei Guang Wu, Cupertino, CA US
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20150341070 | SCREEN PROTECTION USING ACTUATED BUMPERS - An electronic device includes at least one screen. One or more bumpers are moveable between at least a stowed position where the bumper is flush or below the screen and a deployed position where at least a portion of the bumper projects above the screen. One or more sensors detect when the electronic device is subject to one or more drop events. When a drop event is detected, the bumper moves to the deployed position, protecting the screen. In various implementations, the bumper may be moveable by a push-push mechanism or a magnet assisted actuator mechanism. In other implementations, the bumper may include piezoelectric material to which voltage can be applied to move the bumper. | 11-26-2015 |
Weiqing Wu, Cupertino, CA US
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20130305242 | Performance of Load Balancing Modules with Migration Awareness - Embodiments perform migration-aware load balancing in virtual data centers. One or more load balancing modules in a host distribute data requests from clients to one or more servers implemented as virtual machines (VMs). The load balancing modules are notified of VM migration (e.g., live migration) prior to the VM migration and reduce the load on the VM to be migrated. After being notified of completion of VM migration, the load balancing modules increase the load on the migrated VM. Such migration notifications enable the load balancing modules to prevent or reduce performance degradation and migration duration, among other aspects. | 11-14-2013 |
20140376367 | SYSTEM AND METHOD FOR DISTRIBUTION OF POLICY ENFORCEMENT POINT - The disclosure herein describes an edge device of a network for distributed policy enforcement. During operation, the edge device receives an initial packet for an outgoing traffic flow, and identifies a policy being triggered by the initial packet. The edge device performs a reverse lookup to identify at least an intermediate node that is previously traversed by the initial packet and traffic parameters associated with the initial packet at the identified intermediate node. The edge device translates the policy based on the traffic parameters at the intermediate node, and forwards the translated policy to the intermediate node, thus facilitating the intermediate node in applying the policy to the traffic flow. | 12-25-2014 |
20150261556 | LARGE RECEIVE OFFLOAD FOR VIRTUAL MACHINES - A network interface controller (NIC) that includes a set of receive NIC queues capable of performing large receive offload (LRO) operations by aggregating incoming receive packets is provided. Each NIC queue turns on or off its LRO operation based a set of LRO enabling rules or parameters, whereby only packets that meet the set of rules or parameters will be aggregated in the NIC queue. Each NIC queue is controlled by its own set of LRO enabling rules such that the LRO operations of the different NIC queues can be individually controlled. | 09-17-2015 |
20150263968 | SNOOPING FORWARDED PACKETS BY A VIRTUAL MACHINE - A method for performing LRO aggregation on packets being forwarded by a VM is provided. The method segments the LRO aggregated packet according to the Maximum Segment Size (MSS) of the TCP protocol before forwarding the segmented packets to their destination. The method snoops the packets being forwarded for its MSS parameter before using the snooped MSS parameter to perform Transmit Segmentation Offload (TSO) operation. The PNIC performs both the aggregation operation (LRO) and the segmentation (TSO) within its own hardware without consuming CPU cycles at the host machine. The PNIC receives the MSS parameter from the network stack as a metadata that accompanies a LRO aggregated packet. | 09-17-2015 |
20150263974 | LARGE RECEIVE OFFLOAD FOR VIRTUAL MACHINES - A network interface controller (NIC) that includes a set of receive NIC queues capable of performing large receive offload (LRO) operations by aggregating incoming receive packets is provided. Each NIC queue turns on or off its LRO operation based a set of LRO enabling rules or parameters, whereby only packets that meet the set of rules or parameters will be aggregated in the NIC queue. Each NIC queue is controlled by its own set of LRO enabling rules such that the LRO operations of the different NIC queues can be individually controlled. | 09-17-2015 |
Wei-Te Wu, Cupertino, CA US
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20080286979 | Method of controlling sidewall profile by using intermittent, periodic introduction of cleaning species into the main plasma etching species - A method of removing a silicon-containing hard polymeric material from an opening leading to a recessed feature during the plasma etching of said recessed feature into a carbon-containing layer in a semiconductor substrate. The method comprises the intermittent use of a cleaning step within a continuous etching process, where at least one fluorine-containing cleaning agent species is added to already present etchant species of said continuous etching process for a limited time period, wherein the length of time of each cleaning step ranges from about 5% to about 100% of the time length of an etch step which either precedes or follows said cleaning step. | 11-20-2008 |
20090293907 | METHOD OF SUBSTRATE POLYMER REMOVAL - Methods for cleaning a substrate are provided. In one embodiment, the method includes depositing a polymer on a substrate. A cleaning gas is provided to clean a frontside, a bevel edge, and a backside of the substrate. The cleaning gas may include various reactive chemicals such as H | 12-03-2009 |
20140374688 | High Capacity Select Switches for Three-Dimensional Structures - A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line. | 12-25-2014 |
William Wu, Cupertino, CA US
Patent application number | Description | Published |
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20110296122 | METHOD AND SYSTEM FOR BINARY CACHE CLEANUP - A system and method for clearing data from a cache in a storage device is disclosed. The method may include analyzing the cache for the least recently fragmented logical group, and evicting the entries from the least recently fragmented logical group. Or, the method may also include analyzing compaction history and selecting entries for eviction based on the analysis of the compaction history. The method may also include scheduling of different eviction mechanisms during various operations of the storage device. The system may include a cache storage, a main storage and a controller configured to evict entries associated with a least recently fragmented logical group, configured to evict entries based on analysis of compaction history, or configured to schedule different eviction mechanisms during various operations of the storage device. | 12-01-2011 |
20120005405 | Pre-Emptive Garbage Collection of Memory Blocks - A method and system pre-emptively perform garbage collection operations of a forced amount on update blocks in a memory device. The amount of garbage collection needed by a certain data write is monitored and adjusted to match the forced amount if necessary. Update blocks may be selected on the basis of their recent usage or the amount of garbage collection required. Another method and system may store control information about update blocks in a temporary storage area so that a greater number of update blocks are utilized. The sequential write performance measured by the Speed Class test may be optimized by using this method and system. | 01-05-2012 |
20120297118 | FAST TRANSLATION INDICATOR TO REDUCE SECONDARY ADDRESS TABLE CHECKS IN A MEMORY DEVICE - A system and method for reducing the need to check both a secondary address table and a primary address table for logical to physical translation tasks is disclosed. The method may include generating a fast translation indicator, such as a logical group bitmap, indicating whether there is an entry in the secondary address table that contains desired information pertaining to a particular logical address. Upon a host request relating to the particular logical address, the storage device may check the bitmap to determine if retrieval and parsing of the secondary table is necessary. The system may include a storage device having RAM cache storage, flash storage and a controller configured to generate and maintain at least one fast translation indicator to reduce the need to check both secondary and primary address tables during logical to physical address translation operations of the storage device. | 11-22-2012 |
20120297140 | EXPANDABLE DATA CACHE - A method and system for cache management in a storage device is disclosed. A portion of unused memory in the storage device is used for temporary data cache so that two levels of cache may be used (such as a permanent data cache and a temporary data cache). The storage device may manage the temporary data cache in order to maintain clean entries in the temporary data cache. In this way, the storage area associated with the temporary data cache may be immediately reclaimed and retasked for a different purpose without the need for extraneous copy operations. | 11-22-2012 |
20120320679 | SYSTEM AND METHOD FOR MINIMIZING WRITE AMPLIFICATION WHILE MAINTAINING SEQUENTIAL PERFORMANCE USING LOGICAL GROUP STRIPPING IN A MULTI-BANK SYSTEM - A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group. | 12-20-2012 |
20140281132 | METHOD AND SYSTEM FOR RAM CACHE COALESCING - A system and method for coalescing data fragments in a volatile memory such as RAM cache is disclosed. The method may include storing multiple data fragments in volatile memory and initiating a single write operation to flash memory only when a predetermined number of data fragments have been received and aggregated into a single flash write command. The method may also include generating a binary cache index delta that aggregates in a single entry all of the binary cache index information for the aggregated data fragments. A memory system having a non-volatile memory, a volatile memory sized to at least store a number of data fragments equal to a physical page managed in a binary cache of the non-volatile memory, and a controller is disclosed. The controller may be configured to execute the method of coalescing data fragments into a single flash write operation described above. | 09-18-2014 |
William S. Wu, Cupertino, CA US
Patent application number | Description | Published |
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20100172180 | Non-Volatile Memory and Method With Write Cache Partitioning - A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion. | 07-08-2010 |
20100174846 | Nonvolatile Memory With Write Cache Having Flush/Eviction Methods - A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion. | 07-08-2010 |
20100174847 | Non-Volatile Memory and Method With Write Cache Partition Management Methods - A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache. | 07-08-2010 |
20110153912 | Maintaining Updates of Multi-Level Non-Volatile Memory in Binary Non-Volatile Memory - A method of operating a memory system is presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first portion, where data is stored in a binary format, and a second portion, where data is stored in a multi-state format. The controller manages the transfer of data to and from the memory system and the storage of data on the non-volatile memory circuit. The method includes receiving a first set of data and storing this first set of data in a first location in the second portion of the non-volatile memory circuit. The memory system subsequently receives updated data for a first subset of the first data set. The updated data is stored in a second location in the first portion of the non-volatile memory circuit, where the controller maintains a logical correspondence between the second location and the first subset of the first set of data. | 06-23-2011 |
20120297121 | Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions - A non-volatile memory organized into flash erasable blocks receives data from host writes by first staging into logical groups before writing into the blocks. Each logical group contains data from a predefined set of order logical addresses and has a fixed size smaller than a block. The totality of logical groups are obtained by partitioning a logical address space of the host into non-overlapping sub-ranges of ordered logical addresses, each logical group having a predetermined size within a range delimited by a minimum size of at least one page and a maximum size of fitting at least two logical groups in a block and up to an order of magnitude higher than a typical size of a host write. In this way, excessive garbage collection due to operating a large logical group is avoided while the address space is reduced to minimize the size of a caching RAM. | 11-22-2012 |
20120297122 | Non-Volatile Memory and Method Having Block Management with Hot/Cold Data Sorting - A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block. | 11-22-2012 |
20140321202 | DEFECTIVE BLOCK MANAGEMENT - In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations. | 10-30-2014 |
Yihui Wu, Cupertino, CA US
Patent application number | Description | Published |
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20080219160 | PROGRAMMABLE HARDWARE-BASED TRAFFIC POLICING - A hardware-based technique for policing traffic in a network node involves programming a set of algorithm-specific policing primitives that establishes a relationship between condition primitives and action primitives and populating a searchable memory with a set of indexed action primitives. Action primitives are then selected from the searchable memory in response to condition primitives related to a received datagram. Policing actions related to the datagram are performed in response to the action primitive. Because the algorithm-specific policing primitives are programmable, a network node can be adapted to implement a wide variety of policing algorithms. Additionally, multiple different policing algorithms can be implemented in hardware without the need for a different set of combinational logic for each different policing algorithm. | 09-11-2008 |
Yonghui Wu, Cupertino, CA US
Patent application number | Description | Published |
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20140280864 | Methods of Representing Software Defined Networking-Based Multiple Layer Network Topology Views - A method for network control, comprising receiving a request for a network view from an application at a Software Defined Network (SDN) controller, creating a network view from a network map, wherein the network map comprises a representation of a plurality of network devices and network paths in a SDN-based multiple layer network, and wherein the network view comprises at least a portion of the devices or paths in the network map, and sharing the network view with the application. | 09-18-2014 |
Yunxiang Wu, Cupertino, CA US
Patent application number | Description | Published |
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20140026003 | FLASH MEMORY READ ERROR RATE REDUCTION - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust the reference voltage based on a plurality of parameters to lower an error rate in a second read of the set from the memory circuit. The second circuit may be configured to update the parameters in response to an error correction applied to the set after the first read from the memory circuit. The memory circuit is generally configured to store the data in a nonvolatile condition by adjusting a plurality of threshold voltages. | 01-23-2014 |
20140040530 | MIXED GRANULARITY HIGHER-LEVEL REDUNDANCY FOR NON-VOLATILE MEMORY - Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead. | 02-06-2014 |
20140040531 | SINGLE-READ BASED SOFT-DECISION DECODING OF NON-VOLATILE MEMORY - A Solid-State Disk (SSD) controller performs soft-decision decoding with a single read, thus improving performance, power, and/or reliability of a storage sub-system, such as an SSD. In a first aspect, the controller generates soft-decision metrics from channel parameters of a hard decode read, without additional reads and/or array accesses. In a second aspect, the controller performs soft decoding using the generated soft-decision metrics. In a third aspect, the controller generates soft-decision metrics and performs soft decoding with the generated soft-decision metrics when a hard decode read error occurs. | 02-06-2014 |
20140040704 | SOFT-DECISION COMPENSATION FOR FLASH CHANNEL VARIATION - In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation. | 02-06-2014 |
20140164868 | FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE - An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure. | 06-12-2014 |
20140181617 | MANAGEMENT OF NON-VALID DECISION PATTERNS OF A SOFT READ RETRY OPERATION - An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) a value retrieved from a look-up table, and (ii) an index signal. The second circuit may be configured to generate the index signal in response to a plurality of page signals. The apparatus may manage decision patterns during a soft retry. | 06-26-2014 |
20140219028 | Compensation Loop for Read Voltage Adaptation - The disclosure is directed to a system and method for nominal read voltage variations of a flash device. N reads are performed, each at a selected voltage offset from an initial read voltage. An N bit digital pattern associated with the selected voltage offsets is generated for the N reads. The N bit digital pattern generated by the N reads is mapped to a signed representation. A voltage adjustment based upon the signed representation is applied to at least partially compensate for a variation of the nominal read voltage to reduce bit error rate of the flash device. | 08-07-2014 |
20140233322 | ADAPTIVE ARCHITECTURE IN A CHANNEL DETECTOR FOR NAND FLASH CHANNELS - An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether the read is successful, (iii) if the read is not successful, perform a plurality of reads with a varying value of the threshold voltage, (iv) read a calibration value from a look-up table based on the plurality of reads and (v) set the threshold value in response to the calibration value. | 08-21-2014 |
20140241056 | REDUCED COMPLEXITY RELIABILITY COMPUTATIONS FOR FLASH MEMORIES - Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (LLRs), with reduced complexity for flash memory devices. Data from a flash memory device that stores M bits per cell using 2̂M possible states is processed by obtaining at least two soft read voltage values corresponding to two reference voltages V | 08-28-2014 |
20140281767 | RECOVERY STRATEGY THAT REDUCES ERRORS MISIDENTIFIED AS RELIABLE - A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window; and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and (D) if the first, second and third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages to values corresponding to different ones of (i) a point between the left-hand limit and the point central to the read window and (ii) a point between the right-hand limit and the point central to the read window. | 09-18-2014 |
20140281822 | METHOD AND APPARATUS FOR GENERATION OF SOFT DECISION ERROR CORRECTION CODE INFORMATION - A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision information provided by the lookup table and assigned to the appropriate cells of the flash memory device. | 09-18-2014 |
20140286102 | Method of Optimizing Solid State Drive Soft Retry Voltages - A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER. | 09-25-2014 |
20140289450 | Dynamic Log Likelihood Ratio Quantization for Solid State Drive Controllers - A method for system for dynamic channel Log Likelihood Ratio (LLR) quantization for a Solid State Drive (SSD) controller is a targeted approach to scaling which results in a scaled, quantized set of LLRs whose relative magnitude remains undisturbed from an original magnitude. The method reads a set of voltages from each channel of the SSD. The set of reads is configured in location and number for performance. Once a set is returned, the method determines an LLR for each of the voltages read resulting in a raw set of LLRs. Targeted scaling results in a scaled set of LLRs between an upper limit and a lower limit determined for reading by a decoder. Once scaled, the LLRs are rounded and quantized for use by the decoder to produce an Error Correction Code (ECC). | 09-25-2014 |
20150082121 | METHOD OF ERASE STATE HANDLING IN FLASH CHANNEL TRACKING - An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters. | 03-19-2015 |
20150092489 | FLASH MEMORY REFERENCE VOLTAGE DETECTION WITH TRACKING OF CROSS-POINTS OF CELL VOLTAGE DISTRIBUTIONS USING HISTOGRAMS - Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations. | 04-02-2015 |
20150113205 | Systems and Methods for Latency Based Data Recycling in a Solid State Memory System - Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. | 04-23-2015 |
20150113318 | Systems and Methods for Soft Data Utilization in a Solid State Memory System - Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. | 04-23-2015 |
20150113354 | GENERATING SOFT DECODING INFORMATION FOR FLASH MEMORY ERROR CORRECTION USING HARD DECISION PATTERNS - A flash memory controller having soft-decoding error correcting code (ECC) logic generates log likelihood ratio or similar ECC decoder soft input information from decision patterns obtained from reading data from the same portion of flash memory two or more times. Each decision pattern corresponds to a voltage region bordering one of the reference voltages. Each decision pattern represents a combination of flash memory bit value decisions for a cell voltage within the voltage region corresponding to the decision pattern when a corresponding combination of the reference voltages are used to read the cell. Numerical values are then computed in response to combinations of the flash memory bit value decisions represented by the decision patterns. The numerical values are provided to the soft-decoding ECC logic to serve as soft input information. | 04-23-2015 |
20150117097 | Systems and Methods for Sub-Zero Threshold Characterization in a Memory Cell - Systems and method relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. | 04-30-2015 |
20150131373 | Incremental Programming Pulse Optimization to Reduce Write Errors - In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a threshold number of cycles is reached or length of retention or read frequency are anticipated, the cell is programmed using more program voltage pulses, narrower program voltage pulses or some other modification to the incremental step programming pulse to reduce the range where the intermediate least significant (lower) bit read voltage may be erroneous, thereby reducing the probability of write errors when the most significant page (upper) is programmed. | 05-14-2015 |
20150135031 | DYNAMIC PER-DECODER CONTROL OF LOG LIKELIHOOD RATIO AND DECODING PARAMETERS - An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information. | 05-14-2015 |
20150135032 | Detection/Erasure of Random Write Errors Using Converged Hard Decisions - A low-density parity-check decoder in a system with multi-level cells identifies zones of reliability where write errors or stuck cells are identifiable. The system uses assumedly successfully decoded pages associated with bits in a cell to identify candidate write errors or stuck cells and erases a corresponding log-likelihood ratio even where such log-likelihood ratio is saturated, thereby breaking a potential trapping set without post-processing. | 05-14-2015 |
20150143202 | Systems and Methods for Soft Decision Generation in a Solid State Memory System - Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. | 05-21-2015 |
20150149698 | ELIMINATING OR REDUCING PROGRAMMING ERRORS WHEN PROGRAMMING FLASH MEMORY CELLS - Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur. | 05-28-2015 |
20150149856 | DECODING WITH LOG LIKELIHOOD RATIOS STORED IN A CONTROLLER - An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values. | 05-28-2015 |
20150154070 | MIXED GRANULARITY HIGHER-LEVEL REDUNDANCY FOR NON-VOLATILE MEMORY - Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead. | 06-04-2015 |
20150162057 | MULTIPLE RETRY READS IN A READ CHANNEL OF A MEMORY - An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads. | 06-11-2015 |
20150178149 | METHOD TO DISTRIBUTE USER DATA AND ERROR CORRECTION DATA OVER DIFFERENT PAGE TYPES BY LEVERAGING ERROR RATE VARIATIONS - An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types. | 06-25-2015 |
20150178152 | PREVENTING PROGRAMMING ERRORS FROM OCCURRING WHEN PROGRAMMING FLASH MEMORY CELLS - Mis-programming of MSB data in flash memory is prevented by using ECC decoding logic on the flash die that error corrects the LSB values prior to the LSB values being used in conjunction with the MSB values to determine the proper reference voltage ranges. Error correcting the LSB page data prior to using it in combination with the MSB page data to determine the reference voltage ranges ensures that the reference voltage ranges will be properly determined and programmed into the flash cells. | 06-25-2015 |
20150199140 | INTERLEAVING CODEWORDS OVER MULTIPLE FLASH PLANES - An apparatus having an interface to a plurality of memories and a circuit is disclosed. Each memory generally has a plurality of planes and is nonvolatile. The circuit is configured to (i) generate a plurality of codewords by encoding a plurality of data units, (ii) generate a plurality of slices by parsing the codewords, (iii) generate a plurality of pages by interleaving the slices and (iv) write the pages in parallel into respective ones of the planes. | 07-16-2015 |
20150220388 | Systems and Methods for Hard Error Reduction in a Solid State Memory Device - Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory. | 08-06-2015 |
20150227418 | HOT-READ DATA AGGREGATION AND CODE SELECTION - An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory. | 08-13-2015 |
20150235705 | SYSTEM TO CONTROL A WIDTH OF A PROGRAMMING THRESHOLD VOLTAGE DISTRIBUTION WIDTH WHEN WRITING HOT-READ DATA - An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to write user data using a plurality of threshold voltages. The data considered hot-read data is written using a first voltage threshold. The data not considered hot-read data is written using a second voltage threshold. The first voltage threshold reduces an impact on endurance of the memory. | 08-20-2015 |
20150242268 | PERIODICALLY UPDATING A LOG LIKELIHOOD RATIO (LLR) TABLE IN A FLASH MEMORY CONTROLLER - Log likelihood ration (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die. | 08-27-2015 |
20150243363 | ADJUSTING LOG LIKELIHOOD RATIO VALUES TO COMPENSATE MISPLACEMENT OF READ VOLTAGES - An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values. | 08-27-2015 |
20150278015 | FLASH MEMORY READ ERROR RECOVERY WITH SOFT-DECISION DECODE - An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures. | 10-01-2015 |
20150286523 | Systems and Methods for Differential Message Scaling in a Decoding Process - Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit. | 10-08-2015 |
20150286528 | ERROR CORRECTION CODE (ECC) SELECTION IN NAND FLASH CONTROLLERS WITH MULTIPLE ERROR CORRECTION CODES - An apparatus includes an error correction code circuit and an error correction code selection circuit. The error correction code circuit may be configured to encode and decode data using any of a plurality of error correction codes. The error correction code selection circuit may be configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode data responsive to one or more reliability statistics and predetermined data characterizing distribution properties of each of the plurality of error correction codes. | 10-08-2015 |
20150293808 | SOFT READ HANDLING OF READ NOISE - Aspects of the disclosure pertain to methods and systems that are configured to handle excessive read noise in soft read systems. In an implementation, a method includes determining a number of unexpected patterns of a soft read of a memory cell after a soft decoding failure. The method also includes determining whether the number of unexpected patterns is greater than a threshold number of unexpected patterns. When it is determined that the number of unexpected patterns is greater than the threshold number of unexpected patterns, the method at least one of: performing at least one more soft read of the memory cell with a larger read voltage spacing than an initial read that produced the soft decoding failure; and discarding a result of one or more soft reads of the memory cell and utilizing a remainder of results of respective other soft reads of the memory. | 10-15-2015 |
20150294739 | ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING - A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells. | 10-15-2015 |
20150309872 | DATA RECOVERY ONCE ECC FAILS TO CORRECT THE DATA - An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page. | 10-29-2015 |
20150331748 | METHOD TO DYNAMICALLY UPDATE LLRs IN AN SSD DRIVE AND/OR CONTROLLER - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values. The controller may be configured to count a number of unsatisfied checks if the first error correction code decoding fails. The controller may be configured to generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold. The plurality of measured log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory units. | 11-19-2015 |
20150339189 | FIXED POINT CONVERSION OF LLR VALUES BASED ON CORRELATION - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value. | 11-26-2015 |
20150340100 | FLASH COMMAND THAT REPORTS A COUNT OF CELL PROGRAM FAILURES - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units. The memory units may each have a size less than a total size of the memory. The memory units may include a plurality of cells. The controller may be configured to issue a plurality of program operations to write to one or more of the cells. The controller may be configured to implement a polling status command after each of the program operations to verify programming of each of the cells. A response to each of the polling status commands may be used to report a number of the cells that failed to be programmed. | 11-26-2015 |
20150355838 | ESTIMATING READ REFERENCE VOLTAGE BASED ON DISPARITY AND DERIVATIVE METRICS - An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms. | 12-10-2015 |
20150363264 | CELL-TO-CELL PROGRAM INTERFERENCE AWARE DATA RECOVERY WHEN ECC FAILS WITH AN OPTIMUM READ REFERENCE VOLTAGE - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to recover data stored in the memory determined to exceed a maximum number of errors after performing a first read operation using a first read reference voltage. The controller may perform a second read operation using a second read reference voltage. The controller may identify a victim cell having a threshold voltage in a region between the first read reference voltage and the second read reference voltage. The controller may perform a third read operation on aggressor cells of the victim cell. The controller may perform a fourth read operation using the first read reference voltage with bit-fixed values on the victim cell based on a type of interference from the aggressor cells. | 12-17-2015 |
20150364205 | INTER-CELL INTERFERENCE ESTIMATION BASED ON A PATTERN DEPENDENT HISTOGRAM - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a plurality of reads on a victim cell. The controller may be configured to store measured victim information from the plurality of reads on the victim cell. The controller may be configured to perform one or more reads on a plurality of aggressor cells. The controller may be configured to store measured aggressor information from the one or more reads on the plurality of aggressor cells. The controller may be configured to generate inter-cell interference parameters based on the measured victim information and the measured aggressor information. The controller may be configured to mitigate inter-cell interference based on the inter-cell interference parameters. | 12-17-2015 |
20150370631 | WRITE MAPPING TO MITIGATE HARD ERRORS VIA SOFT-DECISION DECODING - An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states. | 12-24-2015 |
Yuwen Wu, Cupertino, CA US
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20120044519 | NETWORK SCANNER OVERIDE OPTIONS IN A DSM ENVIRONMENT - The systems and method herein provide a design logic that extends Distributed Scan Management (DSM) by integrating the scan setting features of a network scanner with DSM and enhances DSM by providing a means for quickly locating Post Scan Processes (PSP) based on specified search criteria. In this regard, a network scanner is controllable via the PSPs of a DSM protocol. A user interface of the network scanner is operable to receive login information associated with a user that is used to grant access to one or more of the PSPs. The network scanner also includes a storage module operable to store scanner software instructions that direct a processor to determine whether the one or more accessed PSPs have settings that are overrideable and present the one or more accessed PSPs to the user for selection. The user may then override settings of a selected PSP via the user interface. | 02-23-2012 |
Zhonghua Wu, Cupertino, CA US
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20140264904 | UNIFIED PCB DESIGN FOR SSD APPLICATIONS, VARIOUS DENSITY CONFIGURATIONS, AND DIRECT NAND ACCESS - Memory systems and methods for creating the same are disclosed. The memory systems can include pairs of IC packages mounted on either side of a system substrate. Contacts formed on the IC packages can be communicatively coupled with contacts of a paired IC package using vias that extend through the system substrate. The IC packages can further communicate with a controller mounted on one side of the system substrate using the vias as well as conductive traces formed in the system substrate. | 09-18-2014 |
20140264906 | SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS - Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides. | 09-18-2014 |
20150325560 | SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS - Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides. | 11-12-2015 |
Zonghuan Wu, Cupertino, CA US
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20120290555 | Method, System and Apparatus of Hybrid Federated Search - A client device comprising a search module configured to receive a search instruction from a federated search server, query one or more search services based on the search instruction, receive a first search result that comprises one or more search results from one or more search services, send the first search result to the federated search server, and receive a second search result from the federated search server. Also disclosed is a federated search server comprising a search instruction generator configured to send a search instruction to a client device, and a search result consolidator configured to receive a first search result from the client device, wherein the first search result comprises one or more search results and is obtained by the client device from one or more search services. | 11-15-2012 |
20150095303 | Knowledge Graph Generator Enabled by Diagonal Search - A method for building and managing a user-customizable knowledge base, the method comprising acquiring data related to a plurality of entities from a plurality of heterogeneous data sources based on a customized acquisition configuration, wherein the customized acquisition configuration specifies a distinct data wrapper for each of the data sources, extracting entity-related information from the data to form a number of graph databases, and integrating the graph databases by mapping relationships between the entities to create an entity-centric knowledge base. | 04-02-2015 |
20150194146 | Intelligent Conversion of Internet Content - An apparatus comprises a data acquisition module configured to extract raw data, and aggregate the raw data to form aggregated data, a data curation module coupled to the data acquisition module and configured to perform curation of the aggregated data to form curated data, and transform the curated data into structured format data, and a transmitter coupled to the data curation module and configured to transmit the structured format data. A method comprises receiving an instruction to perform at least a portion of videolization for a topic, extracting raw data in response to the instruction, aggregating the raw data to form aggregated data, performing curation of the aggregated data to form curated data, transforming the curated data into structured format data, and transmitting the structured format data. | 07-09-2015 |