Patent application number | Description | Published |
20110087821 | APPARATUS TO ACCESS MULTI-BANK MEMORY - A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made. | 04-14-2011 |
20110202704 | MEMORY CONTROLLER, METHOD OF CONTROLLING MEMORY ACCESS, AND COMPUTING APPARATUS INCORPORATING MEMORY CONTROLLER - A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer. | 08-18-2011 |
20110218795 | SIMULATOR OF MULTI-CORE SYSTEM EMPLOYING RECONFIGURABLE PROCESSOR CORES AND METHOD OF SIMULATING MULTI-CORE SYSTEM EMPLOYING RECONFIGURABLE PROCESSOR CORES - Provided are a simulator of a multi-core system employing reconfigurable processor (RP) cores and a method of simulating a multi-core system employing RP cores. The simulator includes a structure builder to receive a structure definition file defining a structure of a system, select components described in the structure definition file from a component library, and fill a data structure with the selected components to generate a structure model of a multi-core system, and a simulation engine to execute an application program according to the structure model and output the result. | 09-08-2011 |
20110246170 | APPARATUS AND METHOD FOR SIMULATING A RECONFIGURABLE PROCESSOR - A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file. | 10-06-2011 |
20110252179 | APPARATUS AND METHOD FOR ROUTING DATA AMONG MULTIPLE CORES - An apparatus and method for routing data among multicores that is capable of reconfiguring the connection among the multicores are provided. The apparatus includes a configuration information generating unit and at least one switching unit. The configuration information generating unit is configured to generate configuration information that indicates a local network connection among the multicores based on a program counter received from each of the multicores. The at least one switching unit is configured to change a data transfer path among the multicores based on the configuration information. | 10-13-2011 |
20120089808 | MULTIPROCESSOR USING A SHARED VIRTUAL MEMORY AND METHOD OF GENERATING A TRANSLATION TABLE - A multiprocessor using a shared virtual memory (SVM) is provided. The multiprocessor includes a plurality of processing cores and a memory manager configured to transform a virtual address into a physical address to allow a processing core to access a memory region corresponding to the physical address. | 04-12-2012 |
20120092987 | ROUTING APPARATUS AND NETWORK APPARATUS - A routing apparatus and a network apparatus that are capable of improving general system performance by compressing/decompressing data and transmitting the result of the compression/decompression, are provided. The routing apparatus may compress and/or decompress input data, and may transmit the compressed and/or decompressed input data. | 04-19-2012 |
20120113128 | COMPUTING APPARATUS AND METHOD USING X-Y STACK MEMORY - A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis. | 05-10-2012 |
20120124343 | APPARATUS AND METHOD FOR MODIFYING INSTRUCTION OPERAND - Provided are an apparatus and method for modifying an instruction operand. The apparatus includes a first selector configured to receive first instruction operands and a second selector configured to receive second instruction operands. The apparatus also includes a modification unit configured to select a first instruction operand and a second instruction operand, and to modify the selected first instruction operand and the selected second instruction operand to reduce the operand instructions that are input to the first selector and the second selector. | 05-17-2012 |
20120151154 | LATENCY MANAGEMENT SYSTEM AND METHOD FOR MULTIPROCESSOR SYSTEM - A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal. | 06-14-2012 |
20120158394 | SIMULATION APPARATUS AND METHOD FOR MULTICORE SYSTEM - A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules. | 06-21-2012 |
20120221797 | MULTI-PORT CACHE MEMORY APPARATUS AND METHOD - Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache. | 08-30-2012 |
20130067203 | PROCESSING DEVICE AND A SWIZZLE PATTERN GENERATOR - A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations. | 03-14-2013 |
20130089102 | COARSE-GRAINED RECONFIGURABLE ARRAY BASED ON A STATIC ROUTER - Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network. | 04-11-2013 |
20140143441 | CHIP MULTI PROCESSOR AND ROUTER FOR CHIP MULTI PROCESSOR - Provided is a chip multi processor that supports both a packet switching method and a circuit switching method, and a router for the chip multi processor. According to an aspect, the chip multi processor includes a plurality of nodes that each include a router, and a plurality of links formed between the routers. Each of the routers may transfer a first type of data based on packet switching and a second type of data based on circuit switching. | 05-22-2014 |
20140215193 | PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF - Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit. | 07-31-2014 |
20140337849 | APPARATUS AND JOB SCHEDULING METHOD THEREOF - An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance. | 11-13-2014 |
20140359335 | MULTI-CORE APPARATUS AND JOB SCHEDULING METHOD THEREOF - A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores. | 12-04-2014 |
20150084957 | METHOD AND APPARATUS FOR ROUTING DATA AND RECONFIGURING RENDERING UNIT - Provided are method and apparatuses for routing and reconfiguring rendering data, the method for routing including identifying, at a processor, a group of input data, transmitting the input data based on a routing path designated for the identified group, and updating the routing path based on a feedback signal regarding the transmitted data. The method for reconfiguring rendering units including measuring, at a processor, workloads of the rendering units used in rendering a previous frame, and reconfiguring the rendering units during rendering a current frame based on the workloads. | 03-26-2015 |