Patent application number | Description | Published |
20120286429 | Semiconductor Device and Method of Singulating Thin Semiconductor Wafer on Carrier Along Modified Region Within Non-Active Region Formed by Irradiating Energy - A semiconductor device comprises a carrier including an adhesive disposed over the carrier. The semiconductor device further comprises a semiconductor wafer including a plurality of semiconductor die separated by a non-active region. A plurality of bumps is formed over the semiconductor die. The semiconductor wafer is mounted to the carrier with the adhesive disposed around the plurality of bumps. Irradiated energy is applied to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die. The semiconductor wafer is singulated along the modified region by applying stress to the semiconductor wafer. The adhesive is removed from around the plurality of bumps after singulating the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor die comprising through silicon vias. The modified region optionally includes a plurality of vertically stacked modified regions. | 11-15-2012 |
20120326296 | Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure - A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure. | 12-27-2012 |
20120326297 | Semiconductor Device and Method of Forming Protective Coating Over Interconnect Structure to Inhibit Surface Oxidation - A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium. | 12-27-2012 |
20130020713 | Wafer Level Package and a Method of Forming a Wafer Level Package - In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided. | 01-24-2013 |
20130037603 | Method of Forming a Bonded Structure - In an embodiment, a method of forming a bonded structure is provided. The method may include forming at least one first under bump metallurgy (UBM) structure on a first substrate, forming a first gold layer on the at least one first under bump metallurgy structure; forming a tin layer on the first gold layer, forming an indium layer on the tin layer, forming an inhibition layer configured to inhibit oxygen penetration on the indium layer, and forming at least one second under bump metallurgy structure on a second substrate, forming s second gold layer on the at least one second under bump metallurgy structure; and bringing the inhibition layer into contact with the second gold layer at a predetermined temperature to form a resultant intermetallic structure between the first substrate and the second substrate thereby bonding the first substrate to the second substrate and forming the bonded structure. | 02-14-2013 |
20130147036 | Semiconductor Device and Method of Forming UBM Structure on Back Surface of TSV Semiconductor Wafer - A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias. | 06-13-2013 |
20130161824 | Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief - A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer. | 06-27-2013 |
20130228919 | Semiconductor Device and Method of Forming Protective Coating Over Interconnect Structure to Inhibit Surface Oxidation - A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium. | 09-05-2013 |
20140103527 | Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units - A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. | 04-17-2014 |
20140159251 | Semiconductor Device and Method of Forming Low Profile Fan-Out Package with Vertical Interconnection Units - A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias. | 06-12-2014 |
20140264851 | Semiconductor Device and Method of Forming UBM Structure on Back Surface of TSV Semiconductor Wafer - A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias. | 09-18-2014 |
20150054151 | Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure - A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure. | 02-26-2015 |
20150179570 | Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package - A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit. | 06-25-2015 |
20150259194 | Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package - A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure. | 09-17-2015 |
Patent application number | Description | Published |
20100142537 | PACKET TRANSPORT LAYER APPARATUS - There is provided a packet transport layer apparatus. The packet transport layer apparatus can receive frames having different formats via a single port by dividing a single physical port into a plurality of virtual ports according to each frame format, can increase the number of customer virtual local area networks (C-VLANs) and the number of service VLANs (S-VLANs) being usable at the same time by assigning a different component identifier (ID) to each frame format and using the component ID as a factor used in searching a filtering table, and can translate a frame format to be suited to a frame format allocated to a virtual output port. | 06-10-2010 |
20110032649 | ESD PROTECTIVE DEVICE HAVING LOW CAPACITANCE AND STABILITY AND A PREPARING PROCESS THEREOF - An ESD protective device having a low capacitance and stability characteristics constructed by installing a voltage sensitive material between electrodes. The voltage sensitive material comprises a fluorescent substance. The voltage sensitive material may be barium aluminate. The voltage sensitive material may be zinc silicate. The voltage sensitive material may be zinc sulfide. The voltage sensitive material is doped with a metal atom such as Mn, Cu and Eu. The device does not distort a signal wave pattern and have low capacitance of 0.5 pF or lower. | 02-10-2011 |
20110134927 | METHOD FOR TRANSMITTING EXTENDED PROTOCOL MESSAGE TO CONTROL SUBSCRIBER SERVICES OF CONNECTION-ORIENTED ETHERNET - In order to transmit an extended protocol message for the purpose of controlling a service of a connection-oriented Ethernet including a plurality of nodes, when an LSP (Label Switched Path) generation request message is received, a path message including an object for delivery of upstream service frame information and an object modified for the transmission of traffic information of a service frame for downstream traffic policing is generated, the path message including the LSP generation request message. When a second node, one of the plurality of nodes, receives the path message from the first node, it generates a reservation (RESV) message including an object added for the transmission of a downstream service frame information and an object modified for the transmission of traffic information of a service frame for upstream traffic policing in response to the LSP generation request message. | 06-09-2011 |
20130163418 | PACKET TRANSPORT SYSTEM AND TRAFFIC MANAGEMENT METHOD THEREOF - A method of managing traffic of packet transport system according to some embodiments of the inventive concept may include calculating an average queue size of input traffic with reference to a link capacity; and differently applying allowable length and probability of disuse with respect to the calculated average queue size according to marking information with respect to packets of the input traffic. The input traffic includes a CCM packet for OAM. | 06-27-2013 |
20130265880 | METHOD AND DEVICE FOR GMPLS BASED MULTILAYER LINK MANAGEMENT IN A MULTILAYER NETWORK - Provided are a method and apparatus for managing a multilevel link that may calculate a shortest path using a Generalized Multiprotocol Label Switching (GMPLS) control plane only, and may manage a single integrated traffic engineering (TE) link using the GMPLS control plane to control switches for various layers, in a cross layer network environment. | 10-10-2013 |
20140205282 | OPTICAL TRANSCEIVER FOR PERFORMING DATA COMMUNICATION AND OPTICAL LINK MONITORING, AND OPTICAL NETWORK SYSTEM - An optical transceiver and an optical network system for performing a data communication and monitoring an optical link are disclosed. The optical transceiver may simultaneously perform the data communication and monitor the optical link, and a wavelength of an optical signal for the data communication and a wavelength of an optical signal for monitoring the optical link may be differently set. | 07-24-2014 |
20150280813 | APPARATUS AND METHOD FOR DISTINGUISHING AMONG NON-REFLECTIVE FAULTS ON OPTICAL LINK - A method of analyzing an optical link fault includes: determining whether a peak is present on an optical time domain reflectometry (OTDR) trace; in response to a determination that there is the peak on the OTDR trace, determining a fault as a reflective fault; in response to a determination that there is no peak on the OTDR trace, determining that the fault is a non-reflective fault; and reporting the optical link fault analysis result. | 10-01-2015 |
Patent application number | Description | Published |
20090106773 | Method and system for user-friendly forwarding entry management based on inter-process communication - A method and system for user-friendly forwarding entry management based on inter-process communication (IPC) is provided. The system includes a function input unit inputting a command for forwarding entry management; and an automated process unit verifying parameters included in the function to create a user table, extracting information for creating a forwarding entry management table from the user table, and outputting a forwarding entry management message including the extracted information. The method includes inputting a command for forwarding entry management; verifying parameters included in the command; creating a user table using the parameters if the verification is successful; extracting information for creating a forwarding entry management table from the user table; and outputting a forwarding entry management message including the extracted information. | 04-23-2009 |
20090135833 | Ingress node and egress node with improved packet transfer rate on multi-protocol label switching (MPLS) network, and method of improving packet transfer rate in MPLS network system - Provided are an ingress node and an egress node on a Multi-Protocol Label Switching (MPLS) network, with an improved packet transfer rate, and a packet transfer rate improving method in a MPLS network system. By assigning a MPLS label to a destination MAC address of a packet in order to guarantee Quality of Service (QoS), it is possible to distributively transmit packets through a variety of paths on a MPLS network and thus improve a packet transfer rate. | 05-28-2009 |
20130286834 | TRAFFIC MANAGEMENT APPARATUS FOR CONTROLLING TRAFFIC CONGESTION AND METHOD THEREOF - Provided are a traffic management apparatus and method for controlling traffic congestion. The traffic management apparatus includes: a hierarchical queue configured to have a plurality of levels that are hierarchically different from each other; a Weighted Random Early Detection (WRED) management unit configured to allocate different weights to the respective levels, and to calculate a profile for each level; and a hierarchical scheduler configured to manage a packet according to each level, using the calculated profile for each level, thereby controlling traffic congestion. | 10-31-2013 |
20140104599 | METHOD OF IMPROVING PERFORMANCE OF OPTICAL TIME DOMAIN REFLECTOMETER (OTDR) - A method of improving the performance of an optical time domain reflectometer (OTDR) is provided. The method according to an embodiment of the present invention can increase accuracy of a distance of the OTDR through an initial calibration method with respect to the refractive index of an optical fiber, and can accurately detect a fault position and accurately analyze a fault cause through a real-time calibration method with respect to the refractive index of the optical fiber when faults and performance degradation occur. | 04-17-2014 |
20140205279 | DEVICE FOR MONITORING OPTICAL LINK FAULT AND METHOD THEREOF - There are provided a device for monitoring an optical link fault and a method thereof. According to an embodiment of the invention, the device for monitoring an optical link fault and the method thereof apply an optical link fault monitoring signal to an optical link and precisely identify a type of the fault using waveforms of a reflected signal returned from the optical link or a wavelength dependence of reflected signal intensity. | 07-24-2014 |
20140314400 | MULTI-LAYER LINK MANAGEMENT DEVICE, MULTI-LAYER INTEGRATED NETWORK TRANSPORT SYSTEM, AND MULTI-LAYER LINK MANAGEMENT METHOD - A multi-layer link management device, a multi-layer integrated network transport system, and a multi-layer link management method are provided. The multi-layer link management device according to an embodiment of the present invention establishes a traffic engineering link stack integrated into one control plane in a multi-layer network, performs real-time monitoring and integrative management on link failure and performance for each layer, and notifies a neighbor node of failure and performance degradation states of a multi-layer link and integratedly manages the failure and performance degradation states. Thus, it is possible to enhance reliability of a multi-layer network and monitor failure and performance degradation in real time, thereby allowing quick performance diagnosis and management of a system and shortening a path protection switching time. | 10-23-2014 |