Patent application number | Description | Published |
20100155818 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating, a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels. | 06-24-2010 |
20100258852 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed. | 10-14-2010 |
20110058418 | 3D NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction. | 03-10-2011 |
20120211822 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed. | 08-23-2012 |
20130175603 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels. | 07-11-2013 |
20140021567 | MAGNENTIC RESISTANCE MEMORY APPARATUS HAVING MULTI LEVELS AND METHOD OF DRIVING THE SAME - A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed. | 01-23-2014 |
20140021568 | MAGNENTIC RESISTANCE MEMORY APPARATUS HAVING MULTI LEVELS AND METHOD OF DRIVING THE SAME - A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed. | 01-23-2014 |
20140022838 | MAGNENTIC RESISTANCE MEMORY APPARATUS HAVING MULTI LEVELS AND METHOD OF DRIVING THE SAME - A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed. | 01-23-2014 |
20140038313 | SEMICONDUCTOR FABRICATING DEVICE AND METHOD FOR DRIVING THE SAME, AND METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION USING THE SAME - In a method for fabricating a magnetic tunnel junction, a first magnetic layer is formed on a substrate, and a tunnel insulating layer is formed on the first magnetic layer. Subsequently, a second magnetic layer is formed on the tunnel insulating layer. In the method, the first magnetic layer is formed by periodically sputtering a magnetic target while a metal target is continuously sputtered. | 02-06-2014 |
Patent application number | Description | Published |
20090273018 | NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer. | 11-05-2009 |
20090325369 | Semiconductor device and method of fabricating the same - A method of fabricating a semiconductor device includes forming a gate dielectric on a substrate, forming a gate structure on the gate dielectric, the gate structure comprising a stacked layer of a silicon layer and a metal layer, selectively etching the gate structure to form a gate pattern, forming a capping layer surrounding the gate pattern, plasma-treating the capping layer, and performing a gate reoxidation process | 12-31-2009 |
20110165769 | NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer. | 07-07-2011 |
20110250746 | NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer. | 10-13-2011 |
20150092480 | ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a seed layer including conductive hafnium silicate; a first magnetic layer formed over the seed layer; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer. | 04-02-2015 |