Woehrle
Gerd H. Woehrle, Eugene, OR US
Patent application number | Description | Published |
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20090099044 | Nanoparticles and Method to Control Nanoparticle Spacing - Disclosed herein are novel nanoparticles, particularly metal nanoparticles, such as gold nanoparticles. According to one embodiment of a method disclosed herein nanoparticles are functionalized via ligand exchange reactions. Also disclosed is a method for controlling nanoparticle spacing to produce nanoparticle arrays having defined spacing. Such nanoparticles and arrays thereof are particularly useful in nanoelectronics, nanophotonics, catalysis, sensors, and biotaggents. | 04-16-2009 |
20090312565 | Compositions of AU-11 nanoparticles and their optical properties - As demonstrated herein, the ligand exchange chemistry of phosphine-stabilized Au | 12-17-2009 |
Judd Woehrle, San Antonio, TX US
Patent application number | Description | Published |
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20120087234 | METHODS, SYSTEMS AND COMPUTER-READABLE MEDIA FOR CONDUCTING COMMUNICATIONS - The present disclosure relates to methods, systems, and computer-readable media for conducting communications. One method includes determining a context associated with a communication between a first participant and a second participant while the communication is occurring, determining a failure of the communication, and resuming the communication based, at least in part, on the context. | 04-12-2012 |
Matthias Woehrle, Boeblingen GR
Patent application number | Description | Published |
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20080215906 | Method for Fault Tolerant Time Synchronization Mechanism in a Large Scaleable Multi-Processor Computer - Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips. | 09-04-2008 |