Patent application number | Description | Published |
20090002808 | Nonlinear Chirped Pulse Fiber Amplifier With Pulse Compression - A chirped-pulse fiber amplification method and system operates with large nonlinear phase shifts (as large as ˜20π or more). In this regime, the pulse spectrum is modified by strong self-phase modulation and gain shaping. With large-enough nonlinear phase shift, substantial spectral broadening occurs. The amplified spectrum can therefore be much broader than the spectrum that is obtained with small nonlinear phase shifts. The broader spectrum enables the formation of a shorter pulse, and the bandwidth generated in nonlinear chirped-pulse amplification can in fact be exploited to generate shorter pulses. Ultimately, this allows the generation of pulses shorter than the gain-narrowing limit of a fiber amplifier. | 01-01-2009 |
20090128892 | Chirped pulse fiber amplifier - A short-pulse fiber amplifier system ( | 05-21-2009 |
20100020387 | CHIRPED-PULSE QUADRATIC NONLINEARITY-BASED HIGH-ENERGY PULSE COMPRESSOR - A pulse compression technique for compressing femtosecond-duration high-energy pulses first linearly chirps and thus broadens an input pulse before compressing it by nonlinear soliton compression. The technique simultaneously decreases the final compressed pulse duration and improves of the compressed pulse quality. In the preferred embodiment, a linear dispersive delay ( | 01-28-2010 |
20100020834 | QUADRATIC NONLINEARITY-BASED HIGH-ENERGY PULSE COMPRESSOR FOR GENERATING FEW-CYCLE PULSES - A pulse compressor for compressing many-cycle femtosecond-duration high-energy pulses to near-single-cycle durations uses a single quadratic nonlinear crystal. A pulsed laser beam is controlled and its passage is aligned through the quadratic nonlinear crystal such that the detrimental effects of group-velocity mismatch are avoided, while still allowing enough nonlinear phase accumulation for compression to near-single-cycle pulse durations. To do so, the perturbation to nonlinear Schrödinger-type soliton compression due to group-velocity mismatch is minimized which requires that the soliton order must not exceed an optimal value set by the amount of group-velocity mismatch. | 01-28-2010 |
20100142034 | DIVIDED-PULSE AMPLIFICATION OF SHORT PULSES - To avoid harmful nonlinear effects in the amplification of short optical pulses, an initial pulse is divided into a sequence of lower-energy temporally spaced pulses that are otherwise identical to the original pulse. The low-intensity pulses are amplified and then recombined to create a final amplified output pulse. | 06-10-2010 |
20110280263 | SATURABLE ABSORBER USING A FIBER TAPER EMBEDDED IN A NANOSTRUCTURE/POLYMER COMPOSITE AND LASERS USING THE SAME - A saturable absorber (SA) is constructed using a fiber taper embedded in a carbon nanotube/polymer composite. A fiber taper is made by heating and pulling a small part of standard optical fiber. At the taper's waist light is guided by the glass-air interface, with an evanescent field protruding out of the taper. Carbon nanotubes mixed with an appropriate polymer host material are then wrapped around the fiber taper to interact with the evanescent field. Saturable absorption is possible due to the unique optical properties of the carbon nanotubes. The device can be used in mode-locked lasers where it initiates and stabilizes the pulses circulating around the laser cavity. The SA can be used in various laser cavities, and can enable different pulse evolutions such as solitons, self-similar pulses and dissipative solitons. Other applications include but are not limited to optical switching, pulse cleanup and pulse compression. | 11-17-2011 |
20120033690 | GIANT-CHIRP OSCILLATOR FOR USE IN FIBER PULSE AMPLIFICATION SYSTEM - A normal-dispersion fiber laser is operated using parameters in which dissipative solitons exist with remarkably large pulse duration and chirp, along with large pulse energy. A low-repetition-rate oscillator that generates pulses with large and linear chirp can thus replace the standard oscillator, stretcher, pulse-picker and preamplifier in a chirped-pulse fiber amplifier. | 02-09-2012 |
20150030039 | BROADBAND SHORT PULSE FIBER LASERS CAPABLE OF GENERATING OUTPUT SPECTRA BROADER THAN GAIN BANDWIDTH - Implementations and examples of fiber lasers based on fiber laser cavity designs that produce self-similar pulses (“similaritons”) to achieve a pulse spectral bandwidth greater than a gain spectral bandwidth based on a spectral broadening fiber segment and a spectral filter to ensure the proper similariton conditions. | 01-29-2015 |
Patent application number | Description | Published |
20100131498 | AUTOMATED HEALTHCARE INFORMATION COMPOSITION AND QUERY ENHANCEMENT - Certain embodiments of the present invention provide systems and methods for information composition and query enhancement. Certain embodiments provide an information composition and query enhancement system. The system includes a query generation and enhancement engine generating and conducting a query of one or more data sources based on user input and a data context to produce query results. The system also includes an information composition engine assembling the query results to provide a bundle of documents meaningful to the particular user. The system further includes a document summarization engine clustering and summarizing the bundle of documents to provide a content summary in addition to the bundle of documents for output in a presentation to a user. | 05-27-2010 |
20140112437 | SYSTEM AND METHOD FOR CONTROLLING A PORTABLE X-RAY SYSTEM - The subject matter disclosed herein relates to patient imaging systems, and more specifically, to portable X-ray imaging systems. In a first embodiment, a patient imaging system is presented. The patient imaging system includes an X-ray source configured to emit X-rays and a wireless X-ray detector configured to detect the emitted X-rays and acquire patient image data. The patient imaging system also includes an acquisition control system configured to initialize and prepare the patient imaging system for X-ray emission and detection. The acquisition control system is also configured to receive the acquired patient image data from the X-ray detector, and to non-deterministically control the operation of the X-ray source and the wireless X-ray detector. The patient imaging system also includes one or more user interfaces configured to instruct the acquisition control system when a user is ready for the patient imaging system to initialize, to prepare for X-ray emission and detection, and to begin X-ray emission and detection. | 04-24-2014 |
20140189703 | SYSTEM AND METHOD FOR DISTRIBUTED COMPUTING USING AUTOMATED PROVISONING OF HETEROGENEOUS COMPUTING RESOURCES - A system for distributed computing includes a job scheduler module configured to identify a job request including request requirements and comprising one or more individual jobs. The system also includes a resource module configured to determine an execution set of computing resources from a pool of computing resources based on the request requirements. Each computing resource of the pool of computing resources has an application programming interface. The pool of computing resources comprises public cloud computing resources and internal computing resources. The system further includes a plurality of interface modules, where each interface module is configured to facilitate communication with the computing resources using the associated application programming interface. The system also includes an executor module configured to identify the appropriate interface module based on facilitating communication with the execution computing resource and transmit jobs for execution to the execution computing resource using the interface modules. | 07-03-2014 |
20140324908 | METHOD AND SYSTEM FOR INCREASING ACCURACY AND COMPLETENESS OF ACQUIRED DATA - The present disclosure relates to the use of both semantic analysis and statistical text mining to process data records, improving the completeness and accuracy of records so processed. By way of example, a data record may be iteratively processed by text mining using seeds derived from a semantic template and by validating the results based on semantic reasoning based on the semantic template. | 10-30-2014 |
Patent application number | Description | Published |
20090065817 | DIELECTRIC SPACER REMOVAL - The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate. | 03-12-2009 |
20090107956 | Thermal Gradient Control of High Aspect Ratio Etching and Deposition Processes - A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills. | 04-30-2009 |
20090184392 | METHOD AND STRUCTURE FOR FORMING TRENCH DRAM WITH ASYMMETRIC STRAP - A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided. The device structure includes a semiconductor substrate having a deep trench therein; and a first conductive layer and a second conductive layer sequentially disposed on said deep trench, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. | 07-23-2009 |
20090189242 | METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES - Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate. | 07-30-2009 |
20100112800 | CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS - Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates. | 05-06-2010 |
20120142181 | CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS - Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates. | 06-07-2012 |
20120153474 | INTEGRATED CIRCUIT SYSTEM WITH REDUCED POLYSILICON RESIDUE AND METHOD OF MANUFACTURE THEREOF - A method of manufacturing an integrated circuit system includes: providing a substrate; forming a polysilicon layer over the substrate; forming an anti-reflective coating layer over the polysilicon layer; etching an anti-reflective coating pattern into the anti-reflective coating layer leaving an anti-reflective coating residue over the polysilicon layer; and etching the anti-reflective coating residue with an etchant gas mixture comprising hydrogen bromide, chlorine, and oxygen to remove the anti-reflective coating residue for mitigating the formation of a polysilicon protrusion. | 06-21-2012 |
20130043559 | TRENCH FORMATION IN SUBSTRATE - A method includes removing an exposed portion of a first portion of a substrate to define a first trench portion partially defined by the first portion of the substrate and expose a second portion of the substrate, the first portion of the substrate disposed on the second portion of the substrate, the second portion of the substrate including an N+ doped silicon material, and removing a portion the exposed second portion of the substrate with an isotropic etching process to define a second trench portion. | 02-21-2013 |
20130295773 | Method for Simultaneously Forming Features of Different Depths in a Semiconductor Substrate - Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen. | 11-07-2013 |
Patent application number | Description | Published |
20110171582 | Three Dimensional Integration With Through Silicon Vias Having Multiple Diameters - A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure. | 07-14-2011 |
20110171827 | Three Dimensional Integration and Methods of Through Silicon Via Creation - A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure. | 07-14-2011 |
20120190189 | Three Dimensional Integration and Methods of Through Silicon Via Creation - A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure. | 07-26-2012 |
20120190196 | Three Dimensional Integration and Methods of Through Silicon Via Creation - A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure. | 07-26-2012 |
20130237054 | THREE DIMENSIONAL INTEGRATION AND METHODS OF THROUGH SILICON VIA CREATION - A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure. | 09-12-2013 |
Patent application number | Description | Published |
20080233691 | METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS - A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer. | 09-25-2008 |
20090096056 | ON-CHIP COOLING SYSTEMS FOR INTEGRATED CIRCUITS - Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient. | 04-16-2009 |
20090194820 | CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS - A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient. | 08-06-2009 |
20100136800 | ON-CHIP COOLING SYSTEMS FOR INTEGRATED CIRCUITS - Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient. | 06-03-2010 |
20100258875 | CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS - A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region. | 10-14-2010 |
20110108895 | METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS - A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer. | 05-12-2011 |
20130012018 | ON-CHIP COOLING FOR INTEGRATED CIRCUITS - A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface. | 01-10-2013 |