Patent application number | Description | Published |
20090026530 | METHODS OF FABRICATING DUAL FIN STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FINS - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 01-29-2009 |
20100072557 | Semiconductor Constructions - Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C | 03-25-2010 |
20100213172 | Using Positive DC Offset of Bias RF to Neutralize Charge Build-Up of Etch Features - Apparatus, systems and methods for plasma etching substrates are provided. The invention achieves dissipation of charge build-up on a substrate being plasma etched to avoid notching or twisting in high aspect ratio contents and similar features. | 08-26-2010 |
20100327369 | Semiconductor Constructions - Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C | 12-30-2010 |
20110057269 | SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 03-10-2011 |
20120175748 | SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS AND METHODS OF FABRICATION - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 07-12-2012 |
20130220549 | USING POSITIVE DC OFFSET OF BIAS RF TO NEUTRALIZE CHARGE BUILD-UP OF ETCH FEATURES - Apparatus, systems and methods for plasma etching substrates are provided that achieve dissipation of charge build-up on a substrate being plasma etched to avoid notching or twisting in high aspect ratio contents and similar features. Charge build-up on a substrate being etched by plasma etching can be dissipated by a method for etching a substrate, the method comprising: providing a plasma processing chamber comprising a chamber enclosure and a substrate support adapted to support a substrate within the chamber enclosure; supporting a substrate on the substrate support; forming a plasma within the chamber enclosure such that a surface of the substrate is in contact with the plasma; etching the substrate by generating a negative bias on the substrate surface relative to the plasma; and intermittently changing the bias on the substrate surface to positive relative to the plasma. The present method can be integrated into known plasma processing systems. | 08-29-2013 |
20130309839 | METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING RECESSES - Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 11-21-2013 |
20140264152 | Chemistry and Compositions for Manufacturing Integrated Circuits - In the manufacture of integrated circuits, reactive compositions that include a reactive etchant species and an oxygen-containing species can provide selective removal of target material and can reduce contamination of gas delivery lines. | 09-18-2014 |
20140273462 | Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells - Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities. | 09-18-2014 |
20150140753 | Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells - Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening. | 05-21-2015 |
Patent application number | Description | Published |
20100110813 | PRECHARGE CONTROL CIRCUITS AND METHODS FOR MEMORY HAVING BUFFERED WRITE COMMANDS - Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed. | 05-06-2010 |
20100250874 | APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY - Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command. | 09-30-2010 |
20110026345 | PRECHARGE CONTROL CIRCUITS AND METHODS FOR MEMORY HAVING BUFFERED WRITE COMMANDS - Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed. | 02-03-2011 |
20120324179 | APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY - Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command. | 12-20-2012 |
20150135038 | POST PACKAGE REPAIR OF MEMORY DEVICES - Apparatuses and methods for post package repair are disclosed. An apparatus can include memory cells in a package. A storage element can store information responsive to a post-package repair mode being activated. The information can identify an address mapped to a portion of the memory cells to be repaired. The storage element can store the information responsive to data received from nodes of the package. A walking token circuit can interrogate the information stored in the storage element in a serial fashion responsive to the post-package repair mode being activated. A mapping circuit can remap, responsive to the interrogation, the address to be repaired to another portion of the memory cells. | 05-14-2015 |
Patent application number | Description | Published |
20080203443 | Independently-Double-Gated Transistor Memory (IDGM) - Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F | 08-28-2008 |
20110147806 | Double-Gated Transistor Memory - Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F | 06-23-2011 |
20110147807 | Single Transistor Memory with Immunity to Write Disturb - Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells using one transistor to implement a Ferroelectric FeRAM are described. Top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F | 06-23-2011 |
20140219604 | Flexible 3-D Photonic Device - Three-dimensional flexible photonic integrated circuits on silicon are fabricated in semiconductor wafer form and then transferred to Silicon-on-Polymer (SOP) substrates. SOP provides flexibility for conformal mounting with devices capable of maintaining performance when dynamically deformed to allow routing of light in x, y and z directions. Bonding a wafer or individual die of III-V semiconductor, such as Gallium Arsenide or similar photonic material, to the flexible silicon creates an active region for lasers, amplifiers, modulators, and other photonic devices using standard processing. Mounting additional photonic devices to the opposite side of a flexible photonic waveguide produces a stack for three-dimensional devices. Multiple flexible photonic waveguides may be stacked to increase functionality by transferring light between stacked waveguides. The flexible photonic circuit allows for integration of photonic devices such as low threshold lasers, tunable lasers, and other photonic integrated circuits with flexible Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. | 08-07-2014 |
20140264938 | Flexible Interconnect - The described Flexible Interconnect is useful for making electrical or other contact between various combinations of semiconductor die, printed circuit boards and other components. A thin flexible material, such as a polymer, supports printed lines that connect pads which may contain vias. The flexible interconnect can be attached using conductive and non-conductive epoxies to the components that are to be interconnected. Each interconnect can be individually insulated from adjacent interconnects, so that it can be deformed and flexed without making contact with another. The described interconnects can span long distances and conform to underlying topography. Metal interconnects may be used to conduct heat or to form heat sinks. Similarly, flexible interconnects may be formed from material that is an electrical insulator but thermally conductive in order to transport heat away from the attached circuitry. Optical conductors may be supported for use as flexible photonic waveguides. | 09-18-2014 |
Patent application number | Description | Published |
20110204648 | WINDMILL WITH BLADES WITH PASSAGEWAYS FROM HUB TO TIP - The present invention is a windmill with blades with passageways for air to move radially outward from near the hub of the windmill to near the tip of the blades. It is thought that the centrifugal force from rotation of the blades will draw or force air into open passageways near the hub of the windmill, and throw the air out forcefully from openings near the tips of the blades. This way, an additional flow of air in or next to and along the blades is created by the rotating additional blades. This additional air flow may be used to move additional generator devices, for example, turbines in an interior space of the windmill support tower, or near the hub of the windmill, or near the tips of the blades. In one embodiment, a funnel shroud near the windmill hub directs additional air from the windward side of the windmill into the proximal end of the passageway near or around the windmill hub. | 08-25-2011 |
20110268572 | HIDE-AWAY WINDMILL - A hide-away windmill is exposed to the wind for use and covered or hidden for storage. In one version, the windmill has a support tower that is extendable and retractable within another housing. In another version, the windmill is inside another housing, and the walls or portions of the housing are movable to open up the housing to expose the windmill to the wind, for example, in a cupola-style housing with louvers or doors. In yet another version, the windmill is surrounded by an extendable and retractable housing, wherein, when the housing is fully retracted, the windmill extends beyond the housing to be exposed to the air and whatever wind is available, and, when the housing is fully extended, the windmill including its turbine blades is entirely or nearly entirely enclosed within the housing. The windmill may be repeatedly exposed to become operable, and repeatedly covered or hidden, not only to become inoperable, but also to be not visible, and protected from high winds, when not in use. The hide-away feature may be for aesthetic reasons, and/or for safety, security and structural reasons. | 11-03-2011 |
20120168047 | CLAMSHELL DOOR HANDLE GRASPER - This invention is a firm bodied, clamshell-like device which is adapted to be easily opened to allow a user to conveniently grasp a door handle. Preferably, the clamshell has a hinge, or an easily repeatably foldable section, at or near its proximal end. Extending distally from the hinge section are generally planar both top and bottom plates. The plates may be relatively flat or curved. An easily operated lock/unlock latch may be located in the hinge. Alternately, a latch may be provided on the distal end of either the top or bottom plates, or along a side of either or both. | 07-05-2012 |
20140102442 | FACIAL ACCESSORY SYSTEM - A facial accessory system for prophylactic face protection. The system includes a facial accessory configured to be worn about the face of a user. The facial accessory include a channel disposed therethrough in fluid communication with an array of apertures orientated and positioned to generate a substantially continuous curtain of airflow about a face of a user when air is forced therethrough. The system includes an airflow distribution device in fluid communication with the channel of the facial accessory. The airflow distribution device is configured to selectively force air to flow therethrough. | 04-17-2014 |
20140290157 | WINDOW AS SOLAR HVAC PORTAL - Described are a cooperating solar energy collector panel and an energy converter, at least one of which is adapted to fit within a window opening. Preferably, the solar collector panel and/or energy converter are movable into or within the window opening to allow for the window to still be able to open to let in fresh air, or be free from obstruction to permit entry of light or a view to the outdoors when the solar collector panel and/or energy converter are not in use. In one version, the solar collector panel is adapted to be remote from the window opening, for example, on the top of an awning above the window opening. The bottom of the awning in this case may be adapted to contain an energy converter which may be moved into the window opening to distribute heat into a building. | 10-02-2014 |