Patent application number | Description | Published |
20120134889 | Exhaust Treatment Device Insulation System - An exhaust treatment device includes an inner shell and an outer shell. Fibrous insulation is positioned within a flexible container. The insulation is compressed 30 to 80 percent by volume. The flexible container is sealed to maintain a compressed state of the insulation. The flexible container and the compressed insulation are positioned between the inner and outer shells of the exhaust treatment device. | 05-31-2012 |
20140140897 | Loose-Fill Insulation Exhaust Gas Treatment Device and Methods of Manufacturing - An exhaust gas treatment device, which includes an outer layer, an inner layer that is at least in part disposed within the outer layer, and a loose-fill insulation disposed in the volume between the outer layer and the inner layer, where a piece of fiber mat is disposed between the outer layer and the inner layer and forms a barrier that at least partially prevents the loss of the loose-fill insulation from the volume between the outer layer and the inner layer and a manufacturing method that includes placing a loose-fill insulation into the volume of space between an inner layer and an outer layer and positioning a piece of fiber mat between the outer layer and the inner layer to form a barrier that at least partially prevents the loss of the loose-fill insulation from the volume of space between the outer and inner layers. | 05-22-2014 |
20140161677 | Loose-Fill Insulation Exhaust Gas Treatment Device and Methods of Manufacturing - An exhaust gas treatment device, which includes an outer layer, an inner layer that is at least in part disposed within the outer layer, and a loose-fill insulation disposed in the volume between the outer layer and the inner layer, where a piece of fiber mat is disposed between the outer layer and the inner layer and forms a barrier that at least partially prevents the loss of the loose-fill insulation from the volume between the outer layer and the inner layer and a manufacturing method that includes placing a loose-fill insulation into the volume of space between an inner layer and an outer layer and positioning a piece of fiber mat between the outer layer and the inner layer to form a barrier that at least partially prevents the loss of the loose-fill insulation from the volume of space between the outer and inner layers. | 06-12-2014 |
20160047285 | Engine Exhaust After-Treatment System - An engine exhaust after-treatment system including an exhaust passage; an exhaust treatment component housing communicating with the exhaust passage; a pair of baffles spaced apart within the housing; a plurality of exhaust treatment devices positioned between the pair of baffles, each exhaust treatment device including a canister; a plurality of restraining devices fixed between the pair of baffles for positioning each of the canisters between the baffles, each restraining device including at least a portion thereof that is angled relative to an outer surface of the canister such that ends of the restraining device abut the outer surface of the canister at the first end and prevent radial movement of the canister; and a soot blower positioned in the housing upstream of the exhaust treatment devices, the soot blower for dispersing particulate matter deposited on each of the exhaust treatment devices. | 02-18-2016 |
Patent application number | Description | Published |
20110083272 | PATIENT HANDLING DEVICE - A patient handling device, such as a bed, stretcher, cot, or the like, includes a deck on which a patient may lie and which is surrounded by siderails. Control panels may be mounted on the siderails in a staggered fashion to improve the ease of accessing the control panels. A handle assembly may be included near the top of the Fowler section of the deck which allows a pair of handles to be squeezed independently for manual pivoting of the Fowler section. Squeezing one handle does not increase the force required to subsequently squeeze the other handle. The pivoting of the Fowler section may also be carried out automatically through an electrical actuator. The raising of the deck may be carried out through an electrical pump that pumps hydraulic fluid, and which may be activated near the top end of the stroke of a reciprocating pedal. | 04-14-2011 |
20120102648 | PATIENT HANDLING DEVICE - A patient handling device, such as a bed, stretcher, cot, or the like, includes a deck on which a patient may lie and which is surrounded by siderails. Control panels may be mounted on the siderails in a staggered fashion to improve the ease of accessing the control panels. A handle assembly may be included near the top of the Fowler section of the deck which allows a pair of handles to be squeezed independently for manual pivoting of the Fowler section. Squeezing one handle does not increase the force required to subsequently squeeze the other handle. The pivoting of the Fowler section may also be carried out automatically through an electrical actuator. The raising of the deck may be carried out through an electrical pump that pumps hydraulic fluid, and which may be activated near the top end of the stroke of a reciprocating pedal. | 05-03-2012 |
20130111664 | WHEELED CARRIAGE WITH BRAKE LOCK SYSTEM - A wheeled carriage for supporting a patient has a wheeled base having frame members supporting a plurality of caster wheel assemblies and a braking system. A moveable brake lock assembly, a brake lock actuator, and a swivel lock receiver are operatively connected to one of the caster wheel assemblies to define a locking caster wheel assembly. The brake lock assembly comprises an actuating member, a swivel lock member, and a brake member that are interconnected as a unit for simultaneous movement. The brake lock actuator is operable to selectively move the brake lock assembly into an engaged position via engagement with the actuating member such that the swivel lock member engages the swivel lock receiver and the brake member contacts a wheel of the locking caster wheel assembly thereby preventing rotation and swiveling of the wheel. | 05-09-2013 |
Patent application number | Description | Published |
20100316681 | N-ALKYLATED RIFAMPIN - Compounds of the formula: | 12-16-2010 |
20110189256 | REDUCTION OF INFECTION ASSOCIATED WITH MEDICAL DEVICE - Anti-infective articles capable of preventing infection associated with implantation of medical devices include low levels of anti-infective agents, may cover only a fraction of the portion of the medical device and be effective, or may rapidly elute anti-infective agent, without sustained elution, and still be effective. | 08-04-2011 |
20140257318 | Anchor Deployment for Implantable Medical Devices - A tool for deploying an anchor sleeve onto an implantable device includes handle and base members, which may be fitted together by an operator. The operator may select the handle member from a plurality thereof included in a kit; and the base member, also included in the kit, includes a rail segment with which a gripping portion of the selected handle member may be engaged, for example, via guidance from a marked portion of the base member. Once engaged, a deployment tip of the base member is located to move a mounted anchor sleeve from a tubular member of the handle member and onto a body of the device. The tubular member of some tools has a laterally offset distal end portion, on which the corresponding anchor sleeve is mounted; thus, kits including this type of handle member, may include a converter for the base member to facilitate engagement therewith. | 09-11-2014 |
Patent application number | Description | Published |
20090160968 | CAMERA USING PREVIEW IMAGE TO SELECT EXPOSURE - A digital camera comprises an image sensor for providing initial sensor image data and final sensor image data; a lens for exposing the image of a scene onto the image sensor; an exposure control system for adjusting an exposure level of a final image on the image sensor in response to a scene type; and a processor for processing the initial sensor image data to select one of a plurality of scene types, and to process the final sensor image data in response to the scene type. | 06-25-2009 |
20100002145 | ADAPTIVE OPTIMIZATION OF A VIDEO SIGNAL - A video signal includes a plurality of frames of image data. A single frame of image data or multiple frames of image data, one or more reduced resolution frames, or a portion or portions of one or more frames or reduced resolution frames can be analyzed to determine initial statistics. One or more correction operations are then performed on the initial statistics to generate initial correction values. The one or more correction operations include a balance correction operation, a flare correction operation, and a tonal correction operation. After the initial correction values are determined, a temporal filter is applied to the initial correction values to generate final correction values. Optimized image data is then generated by applying the final correction values to image data in one or more frames. | 01-07-2010 |
20100008426 | METHOD, APPARATUS AND SYSTEM FOR CONVERGING IMAGES ENCODED USING DIFFERENT STANDARDS - A method for transforming an image expressed in terms of a first image encoding to a second image encoding, includes converting a set of original scene exposure-factor values into corresponding first and second image encoding values. A transform is then derived between the first image encoding values and the second image encoding values. The transform is then applied to an image encoded in said first image encoding. Examples of different encoding that can be transformed include Rec. 709, sRGB and other known image encoding standards. A system for performing such transformations as well as an electronic device that is capable of performing such transformations are also disclosed. | 01-14-2010 |
20130215314 | CAMERA USING PREVIEW IMAGE TO SELECT EXPOSURE - A digital camera comprises an image sensor for providing initial sensor image data and final sensor image data; a lens for exposing the image of a scene onto the image sensor; an exposure control system for adjusting an exposure level of a final image on the image sensor in response to a scene type; and a processor for processing the initial sensor image data to select one of a plurality of scene types, and to process the final sensor image data in response to the scene type. | 08-22-2013 |
20140105495 | METHOD, APPARATUS AND SYSTEM FOR CONVERGING IMAGES ENCODED USING DIFFERENT STANDARDS - A method for transforming an image expressed in terms of a first image encoding to a second image encoding, includes converting a set of original scene exposure-factor values into corresponding first and second image encoding values. A transform is then derived between the first image encoding values and the second image encoding values. The transform is then applied to an image encoded in said first image encoding. Examples of different encoding that can be transformed include Rec. 709, sRGB and other known image encoding standards. A system for performing such transformations as well as an electronic device that is capable of performing such transformations are also disclosed. | 04-17-2014 |
Patent application number | Description | Published |
20080198699 | METHOD FOR BUILT IN SELF TEST FOR MEASURING TOTAL TIMING UNCERTAINTY IN A DIGITAL DATA PATH - A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines. | 08-21-2008 |
20080198700 | DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE - A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines. | 08-21-2008 |
20080263417 | Efficient Memory Product for Test and Soft Repair of SRAM with Redundancy - Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief. | 10-23-2008 |
20090034345 | Eight Transistor SRAM Cell with Improved Stability Requiring Only One Word Line - An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell. | 02-05-2009 |
20090204762 | Self Test Apparatus for Identifying Partially Defective Memory - A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold. | 08-13-2009 |
20110307747 | MEMORY TESTING SYSTEM - An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block coupled to the first output that compares a first expected value with a first data value received at the first data input and provided to the first ABIST logic block after a first clock is applied to the first latch. The system also includes a second ABIST logic block coupled to the second output that compares a second expected value with a second data value received at the second data input and provided to the second ABIST logic block after a second clock is applied to the second latch. | 12-15-2011 |
20140140157 | Complementary Metal-Oxide-Semiconductor (CMOS) Min/Max Voltage Circuit for Switching Between Multiple Voltages - A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption and electro-migration effects. The voltage selection mechanism comprises cross-coupled circuitry, which comprises a first positive-channel field effect transistor (PFET) and a second PFET. The voltage selection mechanism further comprises diode circuitry, which comprises a third PFET and a fourth PFET. | 05-22-2014 |
20140197863 | PLACEMENT OF STORAGE CELLS ON AN INTEGRATED CIRCUIT - A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value. | 07-17-2014 |
20140201589 | SHARED ERROR PROTECTION FOR REGISTER BANKS - A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism. | 07-17-2014 |
20140201606 | ERROR PROTECTION FOR A DATA BUS - A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells. | 07-17-2014 |
20140208184 | ERROR PROTECTION FOR INTEGRATED CIRCUITS - A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism. | 07-24-2014 |
20150262711 | BUILT-IN TESTING OF UNUSED ELEMENT ON CHIP - Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison. | 09-17-2015 |
20150262713 | BUILT-IN TESTING OF UNUSED ELEMENT ON CHIP - Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison. | 09-17-2015 |