Patent application number | Description | Published |
20100112763 | Semiconductor device including gate stack formed on inclined surface and method of fabricating the same - A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction. | 05-06-2010 |
20110057195 | POLY-SI THIN FILM TRANSISTOR AND ORGANIC LIGHT-EMITTING DISPLAY HAVING THE SAME - A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and the drain disposed at either side of the channel respectively. | 03-10-2011 |
20110263088 | POLY-SI THIN FILM TRANSISTOR AND ORGANIC LIGHT-EMITTING DISPLAY HAVING THE SAME - A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and the drain disposed at either side of the channel respectively. | 10-27-2011 |
20130161587 | GRAPHENE DEVICES AND METHODS OF MANUFACTURING THE SAME - A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer. | 06-27-2013 |