Patent application number | Description | Published |
20150214831 | INVERTER AND CONTROL METHOD THEREOF - The present invention discloses an inverter and a control method thereof. The inverter includes a first bridge leg having a series of first switch, second switch, third switch, fourth switch and fifth switch, and a second first bridge leg having a series of sixth switch, seventh switch, eighth switch, ninth switch, tenth switch. The control method includes steps of synchronously turning on or off the first switch, second switch, ninth switch and tenth switch, controlling that an on/off state of the third switch or eighth switch is complementary to an on/off state of the first switch, second switch, ninth switch and tenth switch, and synchronously turning on or off the fourth switch, fifth switch, sixth switch and seventh switch. | 07-30-2015 |
Patent application number | Description | Published |
20090015339 | APPARATUS, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRACKING INFORMATION IN AN ELECTRIC GRID - An apparatus for rapidly tracking fundamental frequency information in the signal of an electric grid is a cross-coupled phase-lock loop filter (CCPLL) that includes the use of a phase-lock-loop (PLL) apparatus having a plurality individual filters, wherein an input for a first filter in the plurality of individual filters comprises the signal of the electric grid and an output signal from at least a second filter in the plurality of individual filters. A method for using the CCPLL includes applying a signal to the CCPLL and monitoring the output of the CCPLL. Use of the CCPLL may be accomplished or modeled via computer instructions stored on machine readable media. | 01-15-2009 |
20090045782 | POWER CONVERSION SYSTEM - A power conversion system includes two three-level converters, and a phase shifted transformer coupled to the converters. | 02-19-2009 |
20090212564 | Method and apparatus for assembling electrical machines - A method of assembling an electrical machine includes programming at least one processor with a stator flux vector estimation scheme. The electrical machine has a stator at least partially extending around a rotor. The electrical machine is electrically coupled to an electric power system. The electric power system transmits at least one phase of electric power to and from the electrical machine with at least partial power conversion. The stator flux vector estimation scheme is programmed to generate at least one stator back-electromagnetic force (back-EMF) signal and to generate at least one stator flux vector signal using the at least one stator back-EMF signal. The at least one stator flux vector signal at least partially represents an estimated rotor position. The method also includes coupling at least one output device in data communication with the at least one processor. | 08-27-2009 |
20100142237 | SYSTEM AND METHOD FOR CONTROL OF A GRID CONNECTED POWER GENERATING SYSTEM - A system for controlling a grid connected power generating system is provided. The system includes a wind turbine, a converter, a first controller and a second controller. The wind turbine supplies electrical power to a power grid and the converter couples the wind turbine to the power grid. The first controller calculates voltage commands to emulate a phasor back electromotive force behind an inductance. The controller further generates converter switching commands from the voltage commands. The voltage commands include a voltage magnitude reference and an internal frequency reference calculated from a power imbalance between an active power reference and the electrical power. The second controller is used to limit a converter current. | 06-10-2010 |
20110074474 | PHASE-LOCKED-LOOP CIRCUIT - A phase-locked loop circuit comprises a phase error detector for receiving a multi-phase reference signal and a synchronized phase signal of the phase-locked-loop circuit, and for performing a rotational transformation to convert the multi-phase reference signal into two-phase quantities at a synchronous rotation d-q reference frame. A monotonic transfer module receives the two-phase quantities, and generates a monotonic phase error signal which is monotonic when a phase difference between the multi-phase reference signal and the synchronized phase signal ranges from −180 degrees to 180 degrees. A regulator receives the monotonic phase error signal, and generates a synchronized rotation frequency. An integrator receives the synchronized rotation frequency, and generates the synchronized phase signal. | 03-31-2011 |
20110075456 | POWER CONVERSION CONTROL SYSTEM - A power distribution system comprises a power conversion module for performing power conversion between a DC voltage at a DC side and an AC power at an AC side, and a conversion control system. The AC side of the power conversion module is electrically coupled to a grid. The conversion control system includes a phase-locked-loop circuit for receiving a multi-phase reference signal of a grid voltage and for generating a synchronized signal, a regulator for receiving reference commands, a two-phase grid feedback signal, and the synchronized signal and for generating a control signal for the power conversion module, and a phase compensation circuit for receiving the synchronized signal and the multi-phase reference signal of the grid voltage, for obtaining a phase displacement signal, and for generating a phase compensation signal for compensating the reference commands or for compensating the synchronized signal when the phase displacement signal exceeds a threshold value. | 03-31-2011 |
20110128760 | APPARATUS AND METHOD FOR DC/AC SYSTEMS TO RIDE THROUGH GRID TRANSIENTS - A converter system comprises a DC to AC converter, a maximum power point tracking device, and an array-side control. The DC link converts DC from a photovoltaic array to AC for a grid. The maximum power point tracking device is coupled to the array. The array-side control, which is coupled to the DC to AC converter and the device, prevents overvoltage in the DC bus of the DC to AC converter using array voltage and current data from the device and DC bus voltage data from the DC to AC converter during a grid transient by adjusting a maximum power point of the array to increase array voltage. | 06-02-2011 |
20130134710 | SYSTEM AND METHOD FOR CONVERTER SWITCHING FREQUENCY CONTROL - A system for power conversion includes a power converter having switching elements, a detector, and a controller is provided. The detector detects a parameter and provides electrical signals indicative of the parameter. The controller receives the electrical signals transmitted from the detector, and sends commands to instruct the power converter to perform power conversion by operating the switching elements in accordance with switching signals at a different frequency in response to a detection of the system condition. A method for operating the system is also provided. | 05-30-2013 |
Patent application number | Description | Published |
20080310065 | Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filters with TVS - A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region. | 12-18-2008 |
20100244090 | TVS with low capacitance & Forward voltage drop with depleted SCR as steering diode - A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage. | 09-30-2010 |
20110095361 | MULTIPLE LAYER BARRIER METAL FOR DEVICE COMPONENT FORMED IN CONTACT TRENCH - A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer. | 04-28-2011 |
20110220990 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 09-15-2011 |
20120129328 | MULTIPLE LAYER BARRIER METAL FOR DEVICE COMPONENT FORMED IN CONTACT TRENCH - A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer. | 05-24-2012 |
20130228860 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 09-05-2013 |
20140167101 | TVS WITH LOW CAPACITANCE & FORWARD VOLTAGE DROP WITH DEPLETED SCR AS STEERING DIODE - A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage. | 06-19-2014 |
20150194522 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 07-09-2015 |
Patent application number | Description | Published |
20140291764 | ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. Second doped base regions discretely located in a fourth region of a first P-type well region are P-type doped and connected to the external trigger-voltage adjustment circuit. A first N-region is located in the fourth region, surrounding the second doped base regions, and connected to the I/O interface terminal. A second N-region is located in the fourth region, surrounding the first N-region and the second doped base regions, and connected to the ground terminal. | 10-02-2014 |
20140291765 | ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit. The external trigger-voltage adjustment circuit can be configured to pull up an electric potential of the second doped base region when the power supply terminal generates an instantaneous electric potential difference. | 10-02-2014 |
20150137881 | High-Voltage-Tolerant Pull-Up Resistor Circuit - A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input/output (I/O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage. | 05-21-2015 |