Patent application number | Description | Published |
20090051413 | APPARATUS AND METHOD FOR INCREASING CHARGE PUMP EFFICIENCY - A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage. | 02-26-2009 |
20140091272 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a conductive structure. The resistance variable memory structure is over the conductive structure. The resistance variable memory structure includes a first electrode over the conductive structure. A resistance variable layer is disposed over the first electrode. A cap layer is disposed over the resistance variable layer. The cap layer includes a first metal material. A second electrode disposed over the cap layer. The second electrode includes a second metal material different from the first metal material. | 04-03-2014 |
20140131650 | RESISTANCE VARIABLE MEMORY STRUCTURE - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 05-15-2014 |
20140131651 | LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS - A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond a region defined by the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the region defined by the first opening. The second electrode is coupled to a second metal layer using a via that extends through the second opening. | 05-15-2014 |
20140131654 | LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS - A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a spacing layer conformally formed on the resistive layer, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening. | 05-15-2014 |
20140166961 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) AND METHOD OF MAKING - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer. | 06-19-2014 |
20140175365 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND METHOD OF MAKING THE RRAM STRUCTURE - The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region. | 06-26-2014 |
20140175366 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 06-26-2014 |
20140247644 | Resistive Memory Reset - A resistive memory cell includes a switch and a resistive switching device. The switch includes a first terminal connected to a select line and a gate terminal connected to a word line. The resistive switching device is connected between a second terminal of the switch and a bit line. The resistive switching device is resettable by having a positive bias applied to the word line and a negative bias applied to the bit line. | 09-04-2014 |
20140252297 | Resistive Memory Cell Array with Top Electrode Bit Line - A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell. | 09-11-2014 |
20140264222 | Resistive Switching Random Access Memory with Asymmetric Source and Drain - The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer. | 09-18-2014 |
20140264233 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround at least the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
20140264234 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
20140264534 | ARCHITECTURE TO IMPROVE CELL SIZE FOR COMPACT ARRAY OF SPLIT GATE FLASH CELL - Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing isolated source regions that are diffused only in the active regions between the stacked control gate structures. The architecture contains no CS under the isolation region, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. A metal layer is disposed along the semiconductor body above the common source regions to provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. Hence, this particular architecture reduces the resistance and the metal connection over several cells in an array suppresses the area over head. | 09-18-2014 |
20150069315 | RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm. | 03-12-2015 |
20150069316 | RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer. | 03-12-2015 |