Patent application number | Description | Published |
20120241868 | METAL-GATE CMOS DEVICE - A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure. | 09-27-2012 |
20130113027 | Metal Oxide Semiconductor Transistor and Manufacturing Method Thereof - The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface. The present invention further provides a manufacturing method of the MOS transistor. | 05-09-2013 |
20130154012 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench. | 06-20-2013 |
20130200470 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures. | 08-08-2013 |
20130203230 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer. | 08-08-2013 |
20130241003 | FINFET AND FABRICATING METHOD THEREOF - A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided. | 09-19-2013 |
20130252387 | METAL-GATE CMOS DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure. | 09-26-2013 |
20130302976 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench. | 11-14-2013 |
20130313648 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench. | 11-28-2013 |
20140077229 | SEMICONDUCTOR STRUCTURE - A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures. | 03-20-2014 |
20140106557 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench. | 04-17-2014 |
20140295660 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally foamed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench. | 10-02-2014 |
20150137196 | Metal Oxide Semiconductor Transistor and Manufacturing Method Thereof - The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor. | 05-21-2015 |
20150380319 | FIN-SHAPED FIELD-EFFECT TRANSISTOR PROCESS - A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided. | 12-31-2015 |
20160079071 | Manufacturing Method of Metal Oxide Semiconductor Transistor - A manufacturing method of MOS transistor, the MOS transistor includes a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor. | 03-17-2016 |
Patent application number | Description | Published |
20120226843 | Method and Computer System for Processing Data in a Memory - The invention discloses a method for processing data in a memory for a computer system. The method comprises receiving a first interrupt for triggering a first job, backing up data corresponding to a second interrupt in the memory when a priority degree of the first interrupt is higher than a priority degree of the second interrupt corresponding to a second job currently being executed by the computer system, executing the first job corresponding to the first interrupt, and restoring the data corresponding to the second interrupt to the memory after the first job corresponding to the first interrupt is finished and continue executing the second job corresponding to the second interrupt. | 09-06-2012 |
20120287592 | ELECTRONIC DEVICE - An electronic device includes a casing and a battery module removably locked to the casing. The casing includes a connecting wall, two inner side walls connected to opposite ends of the connecting wall and having pillars protruding therefrom, and a first magnetic member disposed at the connecting wall. The battery module includes a first side wall to abut against the connecting wall, and two second side walls connected to two opposite ends of the first sidewall. A second magnetic member is disposed at the first side wall and has a magnetic attraction force with the first magnetic member. Each second side wall is formed with a guiding groove extending along an insertion direction of the battery module for engaging a corresponding pillar. | 11-15-2012 |
20130080755 | METHOD FOR SPEEDING UP THE BOOT TIME OF ELECTRIC DEVICE AND ELECTRIC DEVICE USING THE SAME - A method for speeding up the boot time of an electric device and the electric device are disclosed. The disclosed method includes measuring power consumption of the electric device and determining whether the power consumption is greater than a threshold level, wherein the measuring and the determining steps are executed during a boot process of the electric device. If the power consumption is greater than the threshold level, a connector port controller initialization procedure is performed during the boot process, to initialize the connector port controller accordingly. If the power consumption is not greater than the threshold level, a simplified form of the connector port controller initialization procedure is performed during the boot process, to speed up the boot time. | 03-28-2013 |
20130246678 | VIRTUAL SYSTEM MANAGEMENT MODE DEVICE AND CONTROL METHOD THEREOF - A virtual system management mode device, for processing a system management interrupt signal generated by a special process, includes a transformation unit, a control unit memory, and a control unit. The transformation unit transforms the system management interrupt signal into a virtual system management interrupt signal. The control unit memory stores a plurality of system management interrupt processes. The control unit executes one of the system management interrupt processes according to the virtual system management interrupt signal. | 09-19-2013 |
20140001941 | HINGE MECHANISM AND CLAMSHELL DEVICE THEREOF | 01-02-2014 |
20140143477 | COMPUTER SYSTEM AND DATA RECOVERY METHOD THEREOF - A computer system and a data recovery method are provided. The computer system includes an embedded controller (EC). The data recovery method includes following steps. When the computer system stores data into the EC through a basic input/output system (BIOS), the data is backed up into a non-volatile random access memory (NVRAM) by the BIOS. The EC enters a power-off mode. The data is obtained from the NVRAM and is stored back to the EC after the EC leaves the power-off mode. Accordingly, the EC recovers from the power-off mode. | 05-22-2014 |
20140299457 | KEYBOARD MODULE AND ELECTRONIC DEVICE HAVING THE SAME - A keyboard module adapted to be used in an electronic device. The electronic device has a casing. The casing has a containing opening. The keyboard module contained in the containing opening includes a bottom plate, an elastic component, a cover and a key cap disposed on the elastic component. The bottom plate disposed within the casing has a circuit. The elastic component is disposed on the bottom plate or the circuit. The cover movably disposed in the containing opening is located above the bottom plate. The cover has an opening aligned to the elastic component. A portion of the key cap protrudes from the opening Another portion of the key cap interferes with the opening, such that the key cap resists elasticity of the elastic component and moves to shorten a distance between the key cap and the bottom plate when the cover moves toward the bottom plate. | 10-09-2014 |