Patent application number | Description | Published |
20120267779 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3. | 10-25-2012 |
20130256878 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A die is mounted on die attach surface of the substrate via a conductive pillar bump. The die comprises a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view. | 10-03-2013 |
20130313698 | SEMICONDUCTOR PACKAGE - A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board. | 11-28-2013 |
20140035095 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 02-06-2014 |
20140151867 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 06-05-2014 |
20140191396 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. | 07-10-2014 |
20150061117 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps. | 03-05-2015 |
20150087115 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads. | 03-26-2015 |