Patent application number | Description | Published |
20120267779 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3. | 10-25-2012 |
20130256878 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A die is mounted on die attach surface of the substrate via a conductive pillar bump. The die comprises a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view. | 10-03-2013 |
20130313698 | SEMICONDUCTOR PACKAGE - A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board. | 11-28-2013 |
20140035095 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 02-06-2014 |
20140151867 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 06-05-2014 |
20140191396 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. | 07-10-2014 |
20150061117 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps. | 03-05-2015 |
20150087115 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads. | 03-26-2015 |
20150115429 | SEMICONDUCTOR PACKAGE - A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6. | 04-30-2015 |
20150145113 | SEMICONDUCTOR PACKAGE - A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board. | 05-28-2015 |
20150145127 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. A conductive trace is disposed on the substrate. A conductive pillar bump is disposed on the conductive trace, wherein the conductive bump is coupled to a die. In another configuration, a first conductive trace is disposed on the substrate, and a second conductive trace is disposed on the substrate. In the second configuration, a conductive pillar bump disposed on the second conductive trace, connecting to a conductive bump or a metal pad of the semiconductor die. A first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate, and a die is disposed over the first conductive trace. | 05-28-2015 |
20150262840 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - A method for fabricating a base for a semiconductor package is provided. The method operates by providing a carrier with conductive seed layers on the top surface and the bottom surface of the carrier, forming radio-frequency (RF) devices respectively on the conductive seed layers, laminating a first base material layer and a second base material layer respectively on the conductive seed layers, covering the RF devices, and separating the first base material layer the second base material layer, which contain the RF devices thereon, from the carrier to form a first base and a second base. | 09-17-2015 |
20150264814 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface. | 09-17-2015 |
Patent application number | Description | Published |
20110013399 | Thermal Dispersing Structure for LED or SMD LED lights - A thermal dispersing structure for LED or SMD LED lights is to mount a lamp base on a light head. The lamp base is funnel-shaped and has an interior annular cutout near its top edge. A substrate engages the annular cutout to carry one or multiple LED or SMD LED units at a center or other proper locations. Moreover, a rim is formed on the substrate around the LED or SMD LED units. The substrate has multiple holes defined corresponding to thermal conducting bases under the LED or SMD LED units and defined slightly larger or smaller than the LED thermal conducting base. Additionally, a thermal dispersing body is secured under the substrate and has multiple posts corresponding to the holes of the thermal conducting bases. Each post penetrates the substrate to snugly engage the thermal conducting base so that thermal dispersing efficiency is improved. | 01-20-2011 |
20110013403 | Illumination-Improving Structure for LED or SMD LED lights - An illumination-improving structure for LED or SMD LED lights is to mount a lamp base at a light head. The lamp base is funnel-shaped and has an interior annular cutout near its top edge. A substrate engages the annular cutout to carry one or multiple LED or SMD LED units at a center or other proper locations. Moreover, a rim is formed on the substrate to surround the LED or SMD LED units. The lamp base further has a light-adjusting lens mounted over the LED or SMD LED units. The light-adjusting lens has an outer convex arc performing a plane with edge surface and has an inner concave arc or an inner planar surface. The plane and the outer convex arc are connected in form of sharp angle attachment. The inner concave arc or the inner planar surface are treated with foggy treatment or coated with foggy paper. | 01-20-2011 |
20120014116 | Light-Transmissive Shell Capable Of Intensifying Illuminant And Wide-Angle Light Transmission - A light-transmissive shell capable of intensifying an illuminant and wide-angle light transmission includes a lens body and an extension portion integrally extended from the lens body in a vertical direction or at an acute angle to the vertical direction. The lens body includes an outer top surface structured as a convexity and an inner bottom surface structured as a flat surface or an inner concavity. The extension portion includes an inner surface extending around from the inner bottom surface of the lens body. An arcuate surface is formed as a joint between the inner bottom surface of the lens body and the inner surface of the extension portion. The light emitted by an illuminant is intensified through the lens body and guided into a wide-angle light through the extension portion. | 01-19-2012 |
20120056542 | High Illumination LED Bulb with 360-Degree Full Emission Angle - A high illumination LED bulb with a 360-degree full emission angle includes a transparent lamp seat, a transparent lampshade coupled to lamp seat, a support board disposed in a chamber defined by transparent lamp seat and transparent lampshade, a heat dissipating body supported by support board, and first and second light emitting modules. The first light emitting module includes a first substrate disposed on a face of heat dissipating body and at least one LED disposed on first substrate. The second light emitting module includes a second substrate disposed on another face of heat dissipating body and at least one LED disposed on second substrate. The LEDs on first and second substrates can project upper and lower projection lights respectively, and reflected halo formed by projection of upper projection light on transparent lampshade can form side projected halo, thereby a 360-degree full emission angle projected halo can be formed. | 03-08-2012 |