Patent application number | Description | Published |
20080258309 | Three-dimensional semiconductor device - A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device. | 10-23-2008 |
20080268614 | Wafer Bonding - A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers. | 10-30-2008 |
20080272498 | Method of fabricating a semiconductor device - A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap. | 11-06-2008 |
20080286938 | Semiconductor device and fabrication methods thereof - A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings. | 11-20-2008 |
20090001598 | Formation of Through Via before Contact Processing - The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads. | 01-01-2009 |
20090008794 | Thickness Indicators for Wafer Thinning - A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set. | 01-08-2009 |
20090142903 | CHIP ON WAFER BONDER - The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer. | 06-04-2009 |
20090267105 | LED Device with Embedded Top Electrode - An LED device and a method of manufacturing, including an embedded top electrode, are presented. The LED device includes an LED structure and a top electrode. The LED structure includes layers disposed on a substrate, including an active light-emitting region. A top layer of the LED structure is a top contact layer. The top electrode is embedded into the top contact layer, wherein the top electrode electrically contacts the top contact layer. | 10-29-2009 |
20090272975 | Poly-Crystalline Layer Structure for Light-Emitting Diodes - A structure and method for a light-emitting diode are presented. A preferred embodiment comprises a substrate with a conductive, poly-crystalline, silicon-containing layer over the substrate. A first contact layer is epitaxially grown, using the conductive, poly-crystalline, silicon-containing layer as a nucleation layer. An active layer is formed over the first contact layer, and a second contact layer is formed over the active layer. | 11-05-2009 |
20090273002 | LED Package Structure and Fabrication Method - System and method for packaging an LED is presented. A preferred embodiment includes a plurality of thermal vias located through the packaging substrate to effectively transfer heat away from the LED, and are preferably formed along with conductive vias that extend through the packaging substrate. The thermal vias are preferably in the shape of circles or rectangular, and may either be solid or else may encircle and enclose a portion of the packaging substrate. | 11-05-2009 |
20090283871 | System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack - A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside. | 11-19-2009 |
20090289097 | Wafer Leveling-Bonding System Using Disposable Foils - A leveling-bonding method and an apparatus for performing the same are provided. The method includes providing a bond support for supporting a wafer; providing a bond head over the bond support; dispatching a foil over the wafer; placing the wafer on the bond support; and using the bond support and the bond head to apply a force on the foil and the wafer. | 11-26-2009 |
20090311829 | Performing Die-to-Wafer Stacking by Filling Gaps Between Dies - An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die. | 12-17-2009 |
20100001257 | Stress-Alleviation Layer for LED Structures - A light emitting diodes (LEDs) is presented. The LED includes a stress-alleviation layer on a substrate. Open regions and stress-alleviation layer regions are formed on the substrate. Epitaxial layers are disposed on the substrate, at least in the open regions therein, thereby forming an LED structure. The substrate is diced through at least a first portion of the stress-alleviation regions, thereby forming the plurality of LEDs. | 01-07-2010 |
20100001302 | Group-III Nitride for Reducing Stress Caused by Metal Nitride Reflector - A device structure includes a substrate; a group-III nitride layer over the substrate; a metal nitride layer over the group-III nitride layer; and a light-emitting layer over the metal nitride layer. The metal nitride layer acts as a reflector reflecting the light emitted by the light-emitting layer. | 01-07-2010 |
20100009518 | Particle Free Wafer Separation - A method for singulating semiconductor wafers is disclosed. A preferred embodiment comprises forming scrub lines on one side of the wafer and filling the scrub lines with a temporary fill material. The wafer is then thinned by removing material from the opposite side of the wafer from the scrub lines, thereby exposing the temporary fill material on the opposite side. The temporary fill material is then removed, and the individual die are removed from the wafer. | 01-14-2010 |
20100012954 | Vertical III-Nitride Light Emitting Diodes on Patterned Substrates with Embedded Bottom Electrodes - A light emitting diode (LED) device is presented. The LED device includes a substrate, a layered LED structure, and an embedded bottom electrode. The layered LED structure includes a buffer/nucleation layer disposed on the substrate, an active layer, and a top-side contact. A first-contact III-nitride layer is interposed between the buffer/nucleation layer and the active layer. A second-contact III-nitride layer is interposed between the active well layer and the top-side contact. A bottom electrode extends through the substrate, through the buffer/nucleation layer and terminates within the first-contact III-nitride layer. | 01-21-2010 |
20100015782 | Wafer Dicing Methods - Semiconductor wafer dicing methods are disclosed. These methods include forming etch patterns between adjacent semiconductor dice to be separated. Various etch processes can be used to form the etch patterns. The etch patterns generally reach a pre-determined depth into the wafer substrate significantly beyond the wafer top layer where pre-fabricated semiconductor dice are embedded. Semiconductor dice may be separated from a post-etch, large-sized, frangible wafer through wafer grinding, mechanical cleaving, and laser dicing approaches. Preferred embodiments result in reduced wafer-dicing related device damage and improved product yield. | 01-21-2010 |
20100015787 | Realizing N-Face III-Nitride Semiconductors by Nitridation Treatment - A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition. | 01-21-2010 |
20100032696 | Light-Emitting Diode with Textured Substrate - A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions. | 02-11-2010 |
20100032700 | Light-Emitting Diodes on Concave Texture Substrate - A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency. | 02-11-2010 |
20100032718 | III-Nitride Based Semiconductor Structure with Multiple Conductive Tunneling Layer - A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer. | 02-11-2010 |
20100035416 | Forming III-Nitride Semiconductor Wafers Using Nano-Structures - A method of forming a circuit structure includes providing a substrate; etching the substrate to form nano-structures; and growing a compound semiconductor material onto the nano-structures using epitaxial growth. Portions of the compound semiconductor material grown from neighboring ones of the nano-structures join each other to form a continuous compound semiconductor film. The method further includes separating the continuous compound semiconductor film from the substrate. | 02-11-2010 |
20100038655 | Reflective Layer for Light-Emitting Diodes - A system and method for manufacturing a light-generating device is described. A preferred embodiment comprises a plurality of LEDs formed on a substrate. Each LED preferably has spacers along the sidewalls of the LED, and a reflective surface is formed on the substrate between the LEDs. The reflective surface is preferably located lower than the active layer of the individual LEDs. | 02-18-2010 |
20100038659 | Omnidirectional Reflector - A system and method for manufacturing an LED is provided. A preferred embodiment includes a substrate with a distributed Bragg reflector formed over the substrate. A photonic crystal layer is formed over the distributed Bragg reflector to collimate the light that impinges upon the distributed Bragg reflector, thereby increasing the efficiency of the distributed Bragg reflector. A first contact layer, an active layer, and a second contact layer are preferably either formed over the photonic crystal layer or alternatively attached to the photonic crystal layer. | 02-18-2010 |
20100038661 | Light-Emitting Diode With Non-Metallic Reflector - A light-emitting diode (LED) device is provided. The LED device has a substrate, a reflective structure over the substrate, and an LED structure over the reflective structure. The reflective structure is formed of non-metallic materials. In one embodiment, the reflective structure is formed of alternating layers of different non-metallic materials having different refractive indices. In another embodiment, the reflective structure is formed of alternating layers of high-porosity silicon and low-porosity silicon. In yet another embodiment, the reflective structure is formed of silicon dioxide, which may allow the use of fewer layers. The reflective structure may be formed directly on the same substrate as the LED structure or formed on a separate substrate and then bonded to the LED structure. | 02-18-2010 |
20100038674 | Light-Emitting Diode With Current-Spreading Region - A light-emitting diode (LED) device is provided. The LED device has a lower LED layer and an upper LED layer with a light-emitting layer interposed therebetween. A current blocking layer is formed in the upper LED layer such that current passing between an electrode contacting the upper LED layer flows around the current blocking layer. When the current blocking layer is positioned between the electrode and the light-emitting layer, the light emitted by the light-emitting layer is not blocked by the electrode and the light efficiency is increased. The current blocking layer may be formed by converting a portion of the upper LED layer into a resistive region. In an embodiment, ions such as magnesium, carbon, or silicon are implanted into the upper LED layer to form the current blocking layer. | 02-18-2010 |
20100044719 | III-V Compound Semiconductor Epitaxy Using Lateral Overgrowth - A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps, wherein the III-V compound semiconductor layer overlies a buffer/nucleation layer. | 02-25-2010 |
20100050423 | Apparatus and Method of Substrate to Substrate Bonding for Three Dimensional (3D) IC Interconnects - An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads. | 03-04-2010 |
20100051965 | Carbon-Containing Semiconductor Substrate - A light-emitting diode (LED) device is provided. The LED device is formed on a substrate having a carbon-containing layer. Carbon atoms are introduced into the substrate to prevent or reduce atoms from an overlying metal/metal alloy transition layer from inter-mixing with atoms of the substrate. In this manner, a crystalline structure is maintained upon which the LED structure may be formed. | 03-04-2010 |
20100051972 | Light-Emitting Diode Integration Scheme - A circuit structure includes a carrier substrate, which includes a first through-via and a second through-via. Each of the first through-via and the second through-via extends from a first surface of the carrier substrate to a second surface of the carrier substrate opposite the first surface. The circuit structure further includes a light-emitting diode (LED) chip bonded onto the first surface of the carrier substrate. The LED chip includes a first electrode and a second electrode connected to the first through-via and the second through-via, respectively. | 03-04-2010 |
20100055818 | Light-Emitting Diode on a Conductive Substrate - A light-emitting diode (LED) device is provided. The LED device is formed by forming an LED structure on a first substrate. A portion of the first substrate is converted to a porous layer, and a conductive substrate is formed over the LED structure on an opposing surface from the first substrate. The first substrate is detached from the LED structure along the porous layer and any remaining materials are removed from the LED structure. | 03-04-2010 |
20100059779 | Light-Emitting Diode with Embedded Elements - A light-emitting diode (LED) device is provided. The LED device has a substrate and an LED structure overlying the substrate. Embedded elements are embedded within one or more layers of the LED structure. In an embodiment, the embedded elements include a dielectric material extending through the LED structure such that the embedded elements are surrounded by the LED structure. In another embodiment, the embedded elements only extend through an upper layer of the LED structure, or alternatively, partially through the upper layer of the LED structure. Another conductive layer may be formed over the upper layer of the LED structure and the embedded elements. | 03-11-2010 |
20100062551 | Method of Separating Light-Emitting Diode from a Growth Substrate - A method of forming a light-emitting diode (LED) device and separating the LED device from a growth substrate is provided. The LED device is formed by forming an LED structure over a growth substrate. The method includes forming and patterning a mask layer on the growth substrate. A first contact layer is formed over the patterned mask layer with an air bridge between the first contact layer and the patterned mask layer. The first contact layer may be a contact layer of the LED structure. After the formation of the LED structure, the growth substrate is detached from the LED structure along the air bridge. | 03-11-2010 |
20100068866 | III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate - A method of forming a circuit structure includes providing a substrate; forming recesses in the substrate; forming a mask layer over the substrate, wherein the mask layer covers non-recessed portions of the substrate, with the recesses exposed through openings in the mask layer; forming a buffer/nucleation layer on exposed portions of the substrate in the recesses; and growing a group-III group-V (III-V) compound semiconductor material from the recesses until portions of the III-V compound semiconductor material grown from the recesses join each other to form a continuous III-V compound semiconductor layer. | 03-18-2010 |
20100096760 | Bond Pad Design with Reduced Dishing Effect - An integrated circuit structure includes a semiconductor chip, which further includes a first surface; and a patterned bond pad exposed through the first surface. The patterned bond pad includes a plurality of portions electrically connected to each other, and at least one opening therein. The integrated circuit further includes a dielectric material filled into at least a portion of the at least one opening. | 04-22-2010 |
20100117226 | STRUCTURE AND METHOD FOR STACKED WAFER FABRICATION - A method for fabricating stacked wafers is provided. In one embodiment, the method comprises providing a wafer having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies is provided, each of the die bonded to one of the plurality of semiconductor chips. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material. The non-chip side of the wafer is thinned to an intended thickness. The wafer is then diced to separate the wafer into individual semiconductor packages. | 05-13-2010 |
20100122456 | Integrated Alignment and Bonding System - A method for bonding includes providing a first die and a second die; scanning at least one of the first die and the second die to determine thickness variations of the at least one of the first die and the second die; placing the second die facing the first die with a first surface of the first die facing a second surface of the second die; aligning the first surface and the second surface parallel to each other using the thickness variations; and bonding the second die onto the first die. The step of aligning the first surface and the second surface includes tilting one of the first die and the second die. | 05-20-2010 |
20100140767 | Component Stacking Using Pre-Formed Adhesive Films - A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film. | 06-10-2010 |
20100140805 | Bump Structure for Stacked Dies - A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board. | 06-10-2010 |
20100144068 | High Throughput Die-to-Wafer Bonding Using Pre-Alignment - A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action. | 06-10-2010 |
20100144118 | Method for Stacking Semiconductor Dies - A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer. | 06-10-2010 |
20100164109 | Backside Metal Treatment of Semiconductor Chips - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate. The TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. A silicide layer is over and contacting the RDL. | 07-01-2010 |
20100171197 | Isolation Structure for Stacked Dies - An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed. | 07-08-2010 |
20100187694 | Through-Silicon Via Sidewall Isolation Structure - A system and method for an improved through-silicon via isolation structure is provided. An embodiment comprises a semiconductor device having a substrate with electrical circuitry formed thereon. One or more dielectric layers are formed over the substrate, and an opening is etched into the structure extending from a surface of the one or more dielectric layers through the one or more dielectric layers into the substrate; the opening having sidewalls. A low-K dielectric layer is formed over the sidewalls of the opening. The opening is filled with a conductive material and/or a barrier layer creating a through-silicon via that is isolated from the surrounding substrate by the low-K dielectric layer. | 07-29-2010 |
20100193954 | Barrier Structures and Methods for Through Substrate Vias - Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via. | 08-05-2010 |
20100237502 | Barrier for Through-Silicon Via - A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition. | 09-23-2010 |
20100267217 | Backside Process for a Substrate - A method of forming a semiconductor device is presented. A conductor is embedded within a substrate, wherein the substrate contains a non-conducting material. The backside of the substrate is ground to a thickness wherein at least | 10-21-2010 |
20100314758 | THROUGH-SILICON VIA STRUCTURE AND A PROCESS FOR FORMING THE SAME - A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer. | 12-16-2010 |
20100327463 | STACKED STRUCTURES AND METHODS OF FABRICATING STACKED STRUCTURES - A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure. | 12-30-2010 |
20100330743 | Three-Dimensional Integrated Circuits with Protection Layers - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 12-30-2010 |
20110006428 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 01-13-2011 |
20110065238 | PROTECTION LAYER FOR ADHESIVE MATERIAL AT WAFER EDGE - A wafer is attached to a carrier by using an adhesive layer, and a portion of the adhesive layer is exposed adjacent to an edge of the wafer. After thinning the wafer, a protection layer is provided to cover the exposed portion of the adhesive layer. A plurality of dies is bonded onto the thinned wafer, and then the thinned wafer and the dies are encapsulated with a molding compound. | 03-17-2011 |
20110068466 | Wafer Backside Interconnect Structure Connected to TSVs - An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line. | 03-24-2011 |
20110081749 | SURFACE MODIFICATION FOR HANDLING WAFER THINNING PROCESS - A wafer is provided with a through via extending a portion of a substrate, an interconnect structure electrically connecting the through via, and a polyimide layer formed on the interconnect structure. Surface modification of the polyimide layer is the formation of a thin dielectric film on the polyimide layer by coating, plasma treatment, chemical treatment, or deposition methods. The thin dielectric film is adhered strongly to the polyimide layer, which can reduce the adhesion between the wafer surface and an adhesive layer formed in subsequent carrier attaching process. | 04-07-2011 |
20110177655 | Formation of Through Via before Contact Processing - The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads. | 07-21-2011 |
20110186967 | Component Stacking Using Pre-Formed Adhesive Films - A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film. | 08-04-2011 |
20110189837 | Realizing N-Face III-Nitride Semiconductors by Nitridation Treatment - A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition. | 08-04-2011 |
20110248409 | Method for Stacking Semiconductor Dies - A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer. | 10-13-2011 |
20110277655 | Forming Interconnect Structures Using Pre-Ink-Printed Sheets - A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate. | 11-17-2011 |
20110278732 | Interconnect Structures for Substrate - A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like. | 11-17-2011 |
20110304042 | Copper Bump Structures Having Sidewall Protection Layers - A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer. | 12-15-2011 |
20110309647 | Vacuum Wafer Carriers for Strengthening Thin Wafers - An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage. | 12-22-2011 |
20110316147 | Embedded 3D Interposer Structure - A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump. | 12-29-2011 |
20110316201 | Wafer Level Packaging Using Blade Molding - In accordance with an embodiment, a molding apparatus comprises a screen having a planar top surface; a recess in the screen and extending below the planar top surface; a blade capable of traversing the planar top surface; and a molding compound applicator. Another embodiment is a method for molding. The method comprises providing a substrate in a confined volume with an open top surface, applying molding compound in the confined volume, and traversing the open top surface with a blade thereby forming the molding compound to have a planar surface that is co-planar with the open top surface. The substrate has at least one semiconductor die adhered to the substrate. | 12-29-2011 |
20120001337 | Alignment Mark and Method of Formation - In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess. | 01-05-2012 |
20120007048 | III-Nitride Based Semiconductor Structure with Multiple Conductive Tunneling Layer - A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer. | 01-12-2012 |
20120018876 | Multi-Die Stacking Using Bumps with Different Sizes - A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first side of the first die through the first metal bump. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion encircling the second die, and an opening exposing the second region of the first side of the first die. A second metal bump of a second horizontal size is formed on the second region of the first side of the first die and extending into the opening of the dielectric layer. The second horizontal size is greater than the first horizontal size. An electrical component is bonded to the first side of the first die through the second metal bump. | 01-26-2012 |
20120025222 | Light-Emitting Diode Integration Scheme - A circuit structure includes a carrier substrate, which includes a first through-via and a second through-via. Each of the first through-via and the second through-via extends from a first surface of the carrier substrate to a second surface of the carrier substrate opposite the first surface. The circuit structure further includes a light-emitting diode (LED) chip bonded onto the first surface of the carrier substrate. The LED chip includes a first electrode and a second electrode connected to the first through-via and the second through-via, respectively. | 02-02-2012 |
20120025234 | Light-Emitting Diode with Textured Substrate - A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions. | 02-02-2012 |
20120025368 | Semiconductor Device Cover Mark - A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate. | 02-02-2012 |
20120032348 | THREE-DIMENSIONAL INTEGRATED CIRCUITS WITH PROTECTION LAYERS - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 02-09-2012 |
20120040500 | Semiconductor Molding Chamber - A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer. | 02-16-2012 |
20120045611 | Composite Carrier Structure - A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias. | 02-23-2012 |
20120056315 | Alignment Marks in Substrate Having Through-Substrate Via (TSV) - A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate. | 03-08-2012 |
20120074562 | Three-Dimensional Integrated Circuit Structure with Low-K Materials - A device includes an interposer free from active devices therein. The interposer includes a substrate; a through-substrate via (TSV) penetrating through the substrate; and a low-k dielectric layer over the substrate. | 03-29-2012 |
20120074582 | DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME - A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. | 03-29-2012 |
20120083116 | Cost-Effective TSV Formation - A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other. | 04-05-2012 |
20120104578 | Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. | 05-03-2012 |
20120119236 | Light-Emitting Diodes on Concave Texture Substrate - A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency. | 05-17-2012 |
20120128457 | Reconfigurable Guide Pin Design for Centering Wafers Having Different Sizes - An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports | 05-24-2012 |
20120145204 | Spin Chuck for Thin Wafer Cleaning - A device and system for thin wafer cleaning is disclosed. A preferred embodiment comprises a spin chuck having at least three holding clamps. A thin wafer with a wafer frame is mounted on the spin chuck through a tape layer. When the holding clamps are unlocked, there is no interference with the removal and placement of the wafer frame. On the other hand, when the holding clamps are locked, the holding clamps are brought into contact with the outer edge of the wafer frame so as to prevent the wafer frame from moving laterally. Furthermore, the shape of the holding clamps in a locked position is capable of preventing the wafer frame from moving vertically. | 06-14-2012 |
20120164789 | Three-Dimensional Semiconductor Device - A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device. | 06-28-2012 |
20120187576 | Three-Dimensional Integrated Circuits with Protection Layers - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 07-26-2012 |
20120217611 | INTEGRATED CIRCUITS INCLUDING CONDUCTIVE STRUCTURES THROUGH A SUBSTRATE AND METHODS OF MAKING THE SAME - An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap. | 08-30-2012 |
20120238057 | Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. | 09-20-2012 |
20120289062 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 11-15-2012 |
20120292783 | PROTECTION LAYER FOR ADHESIVE MATERIAL AT WAFER EDGE - This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies. | 11-22-2012 |
20120298956 | Method of Separating Light-Emitting Diode from a Growth Substrate - A method of forming a light-emitting diode (LED) device and separating the LED device from a growth substrate is provided. The LED device is formed by forming an LED structure over a growth substrate. The method includes forming and patterning a mask layer on the growth substrate. A first contact layer is formed over the patterned mask layer with an air bridge between the first contact layer and the patterned mask layer. The first contact layer may be a contact layer of the LED structure. After the formation of the LED structure, the growth substrate is detached from the LED structure along the air bridge. | 11-29-2012 |
20120313247 | Through Silicon Via Structure and Method - A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via. | 12-13-2012 |
20120319291 | SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME - A semiconductor structure includes a dielectric layer disposed over a substrate. A metallic line is disposed in the dielectric layer. A through-silicon-via (TSV) structure continuously extends through the dielectric layer and the substrate. A surface of the metallic line is substantially leveled with a surface of the TSV structure. | 12-20-2012 |
20130001783 | Interconnect Barrier Structure and Method - A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device. | 01-03-2013 |
20130082296 | LED Device with Embedded Top Electrode - An LED device and a method of manufacturing, including an embedded top electrode, are presented. The LED device includes an LED structure and a top electrode. The LED structure includes layers disposed on a substrate, including an active light-emitting region. A top layer of the LED structure is a top contact layer. The top electrode is embedded into the top contact layer, wherein the top electrode electrically contacts the top contact layer. | 04-04-2013 |
20130087908 | BUMP WITH PROTECTION STRUCTURE - A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof. | 04-11-2013 |
20130093098 | THROUGH SUBSTRATE VIA STRUCTURES AND METHODS OF FORMING THE SAME - The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill. | 04-18-2013 |
20130113105 | Barrier For Through-Silicon Via - A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV). | 05-09-2013 |
20130122700 | Multi-Die Stacking Using Bumps with Different Sizes - A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first metal bump at the first side of the first die. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion covering the second die. A second metal bump of a second horizontal size greater than the first horizontal size is formed on the second region of the first side of the first die. An electrical component is bonded to the first side of the first die through the second metal bump. | 05-16-2013 |
20130126946 | III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate - A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask. | 05-23-2013 |
20130133688 | WAFER DEBONDING AND CLEANING APPARATUS AND METHOD OF USE - This description relates to a wafer debonding and cleaning apparatus including an automatic wafer handling module. The automatic wafer handling module loads a semiconductor wafer into a wafer debonding module for a debonding process. The automatic wafer handling module removes the semiconductor wafer from the debonding module and loads the semiconductor wafer into a wafer cleaning module for a cleaning process. | 05-30-2013 |
20130137222 | Method for Stacking Semiconductor Dies - A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer. | 05-30-2013 |
20130140690 | TSV Structures and Methods for Forming the Same - A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. | 06-06-2013 |
20130157412 | CHIP ON WAFER BONDER - The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer. | 06-20-2013 |
20130183831 | Reducing Substrate Warpage in Semiconductor Processing - System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate. | 07-18-2013 |
20130224892 | OMNIDIRECTIONAL REFLECTOR - A system and method for manufacturing an LED is provided. A preferred embodiment includes a substrate with a distributed Bragg reflector formed over the substrate. A photonic crystal layer is formed over the distributed Bragg reflector to collimate the light that impinges upon the distributed Bragg reflector, thereby increasing the efficiency of the distributed Bragg reflector. A first contact layer, an active layer, and a second contact layer are preferably either formed over the photonic crystal layer or alternatively attached to the photonic crystal layer. | 08-29-2013 |
20130224909 | PROCESS OF FORMING THROUGH-SILICON VIA STRUCTURE - In a process, an opening is formed to extend from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A metal silicide layer is formed on at least one portion of the metal seed layer. A metal layer is formed on the metal silicide layer and the metal seed layer to fill the opening. | 08-29-2013 |
20130228920 | PROTECTION LAYER FOR ADHESIVE MATERIAL AT WAFER EDGE - A three-dimensional integrated circuit (3DIC) including a first substrate having a first surface and a second surface opposite to the first surface and a second substrate attached to the first surface of the first substrate. The 3DIC further includes an interconnect between attached to the first surface of the first substrate and the second substrate and a plurality of through vias formed in the first substrate and electrically coupled to the interconnect. The 3DIC further includes a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias protrudes through the protection layer and a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias. | 09-05-2013 |
20130241057 | Methods and Apparatus for Direct Connections to Through Vias - Methods and apparatus for direct connection to a through via. An apparatus includes a substrate having a front side surface and a back side surface; conductive through vias formed in the substrate and having through via protrusions extending from the back side surface; solder connectors on another device and coupling the another device to the substrate, wherein the solder connectors correspond to the through via protrusions and enclose the through via protrusions to form solder joints; and connectors on the front side surface of the substrate for forming additional electrical connections. Methods include providing a substrate with through vias; thinning the substrate; etching the substrate to create through via protrusions; aligning another device with solder connectors on a surface corresponding to the through via protrusions; placing the solder connectors in contact with the protrusions; and performing a thermal reflow to form solder joints around the through via protrusions. | 09-19-2013 |
20130252422 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - In a method of forming a semiconductor structure, a through-silicon-via (TSV) opening is formed in a substrate. A dielectric layer is formed to continuously extend over the substrate and into the TSV opening. At least one conductive material is formed over the dielectric layer and in the TSV opening. A portion of the at least one conductive material that is over the dielectric layer is removed to form a TSV structure in the substrate. A metallic line is formed in the dielectric layer. A portion of the substrate is removed, such that the TSV structure continuously extends through the substrate and the dielectric layer. | 09-26-2013 |
20130264539 | Light-Emitting Diode with Current-Spreading Region - A light-emitting diode (LED) device is provided. The LED device has a lower LED layer and an upper LED layer with a light-emitting layer interposed therebetween. A current blocking layer is formed in the upper LED layer such that current passing between an electrode contacting the upper LED layer flows around the current blocking layer. When the current blocking layer is positioned between the electrode and the light-emitting layer, the light emitted by the light-emitting layer is not blocked by the electrode and the light efficiency is increased. The current blocking layer may be formed by converting a portion of the upper LED layer into a resistive region. In an embodiment, ions such as magnesium, carbon, or silicon are implanted into the upper LED layer to form the current blocking layer. | 10-10-2013 |
20130285200 | Capacitor for Interposers and Methods of Manufacture Thereof - Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate. | 10-31-2013 |
20130285244 | Through Silicon Via with Embedded Barrier Pad - A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like. | 10-31-2013 |
20130299992 | Bump Structure for Stacked Dies - A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board. | 11-14-2013 |
20130309813 | Embedded 3D Interposer Structure - A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump. | 11-21-2013 |
20130316528 | Interconnect Barrier Structure and Method - A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device. | 11-28-2013 |
20130320071 | Apparatus and Method of Substrate to Substrate Bonding for Three Dimensional (3D) IC Interconnects - An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads. | 12-05-2013 |
20130320493 | CAPACITOR FOR INTERPOSERS AND METHODS OF MANUFACTURE THEREOF - Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers. | 12-05-2013 |
20130323883 | DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME - A method includes forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth. The method further includes forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening and forming a conductive layer on the insulation structure to fill the opening. A first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. | 12-05-2013 |
20130323886 | Semiconductor Molding Chamber - A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer. | 12-05-2013 |
20130334832 | Reconfigurable Guide Pin Design for Centering Wafers Having Different Sizes - An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports | 12-19-2013 |
20140027872 | CIS Chips and Methods for Forming the Same - A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL. | 01-30-2014 |
20140061924 | Interconnect Structure and Method - An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line. | 03-06-2014 |
20140077374 | Through Via Structure and Method - An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material. | 03-20-2014 |
20140131884 | Through-Substrate via Formation with Improved Topography Control - A device include a substrate and an interconnect structure over the substrate. The interconnect structure comprising an inter-layer dielectric (ILD) and a first inter-metal dielectric (IMD) formed over the ILD. A through-substrate via (TSV) is formed at the IMD extending a first depth through the interconnect structure into the substrate. A metallic pad is formed at the IMD adjoining the TSV and extending a second depth into the interconnect structure, wherein the second depth is less than the first depth. Connections to the TSV are made through the metallic pad. | 05-15-2014 |
20140166979 | Light-Emitting Diode with Textured Substrate - A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions. | 06-19-2014 |
20140261997 | Selective Curing Method of Adhesive on Substrate - Embodiments of the present disclosure include methods of forming a semiconductor device. An embodiment is a method for forming a semiconductor device, the method including applying a substrate to a carrier with an adhesive layer between the carrier and the substrate, curing a portion of the adhesive layer, the cured portion surrounding an uncured portion of the adhesive layer, removing the carrier from adhesive layer, removing the uncured portion of the adhesive layer, and removing the cured portion of the adhesive layer. | 09-18-2014 |
20140264834 | Low Cost and Ultra-Thin Chip on Wafer on Substrate (CoWoS) Formation - Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer. | 09-18-2014 |
20140327151 | THROUGH SUBSTRATE VIA STRUCTURES AND METHODS OF FORMING THE SAME - A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section. | 11-06-2014 |
20150035159 | SEMICONDUCTOR DEVICE HAVING BACKSIDE INTERCONNECT STRUCTURE ON THROUGH SUBSTRATE VIA AND METHOD OF FORMING THE SAME - A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer. | 02-05-2015 |
20150037960 | METHOD OF MANUFACTURING A CAPACITOR - A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor. | 02-05-2015 |