Patent application number | Description | Published |
20090102520 | DIRECT INJECTION-LOCKED FREQUENCY DIVIDER CIRCUIT WITH INDUCTIVE-COUPLING FEEDBACK ARCHITECTURE - A direct injection-locked frequency divider circuit with inductive-coupling feedback architecture is proposed, which is designed for integration to a high-frequency circuit system with a high operating frequency such as 24 GHz (gigahertz), for providing a frequency-dividing function. The proposed frequency divider circuit comprises an injection-locked oscillator (ILO) circuit module and a pair of buffer-stage circuits, wherein the ILO circuit module further includes a signal-injection circuit, a cross-coupled switching circuit, and a variable-capacitance tuning circuit. The proposed circuit architecture is characterized by the circuit arrangement of a direct-injection architecture and an inductive-coupling feedback architecture by coupling the inductive elements of the buffer-stage circuits to the inductive elements of the variable-capacitance tuning circuit in the ILO circuit module. These features allow the proposed frequency divider circuit to have higher operating frequency with wider frequency locking range, low power consumption, and small integrated circuit layout area. | 04-23-2009 |
20090184769 | NEGATIVE-FEEDBACK TYPE ULTRA-WIDEBAND SIGNAL AMPLIFICATION CIRCUIT - A negative-feedback type ultra-wideband signal amplification circuit is proposed, which is designed for integration to an ultra-wideband (UWB) signal processing circuit system for providing a low-noise amplification function to UWB signals. The proposed circuit architecture is characterized by the provision of a dual-step filter circuit on the input side, the provision of a resistive-type feedback circuit in the transistor-based amplification circuitry, and the provision of a common-source transistor-based amplification circuit on the output side. These features allow the proposed signal amplification circuit to have flat power gain, lower power consumption, low noise figure, and higher operational stability. | 07-23-2009 |
20090189706 | INDUCTANCE-SWITCHABLE DUAL-BAND VOLTAGE CONTROLLED OSCILLATION CIRCUIT - An inductance-switchable dual-band voltage-controlled oscillation circuit is proposed, which is designed for integration to a high-frequency signal processing system, such as an ultra-wideband (UWB) circuit system, for providing a dual-band voltage-controlled oscillating signal generating function. The proposed voltage-controlled oscillation circuit is characterized by the use of a switchable inductance circuit architecture in lieu of a switchable capacitive circuit architecture for integration to a fixed-inductance circuit architecture to constitute a variable-inductance LC tuning circuit architecture that allows the provision of a dual-band oscillating signal generating function. Further, a current mirror circuit module is used to maintain the quality factor of the LC tuning circuit in both operating modes; a buffer-stage circuit architecture is used to achieve low power consumption, low phase noise, and broad tuning range. | 07-30-2009 |
20110159678 | METHOD TO FORM A SEMICONDUCTOR DEVICE HAVING GATE DIELECTRIC LAYERS OF VARYING THICKNESSES - A method for fabricating an integrated circuit device is disclosed. An exemplary method can include providing a substrate having a first region, a second region, and a third region; and forming a first gate structure in the first region, a second gate structure in the second region, and a third gate structure in the third region, wherein the first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region. | 06-30-2011 |
20110306196 | METHOD TO FORM A SEMICONDUCTOR DEVICE HAVING GATE DIELECTRIC LAYERS OF VARYING THICKNESS - A method for fabricating an integrated circuit device is disclosed which includes providing a substrate having first, second, and third regions; and forming first, second, and third gate structures in the first, second, and third regions, respectively. The first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region. | 12-15-2011 |
Patent application number | Description | Published |
20110143529 | METHOD OF FABRICATING HIGH-K/METAL GATE DEVICE - The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench. | 06-16-2011 |
20110256682 | Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device - A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment includes a UV radiation in the presence of O | 10-20-2011 |
20110256731 | METHOD FOR FABRICATING A GATE DIELECTRIC LAYER - A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer. | 10-20-2011 |
20120261758 | METHOD OF FABRICATING A GATE DIELECTRIC LAYER - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate having a first active region; a first gate structure over the first active region, wherein the first gate structure comprises a first interfacial layer having a convex top surface; a first high-k dielectric over the first interfacial layer; and a first gate electrode over the first high-k dielectric. | 10-18-2012 |
20120264281 | METHOD OF FABRICATING A PLURALITY OF GATE STRUCTURES - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode. | 10-18-2012 |
20130032900 | BUFFER LAYER AND METHOD OF FORMING BUFFER LAYER - Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer. | 02-07-2013 |
20130040455 | HIGH TEMPERATURE ANNEAL FOR STRESS MODULATION - A method for modulating stress in films formed in semiconductor device manufacturing provides for high temperature annealing of an as-deposited compressive film such as titanium nitride. The high temperature annealing converts the initially compressive film to a tensile film without compromising other film qualities and characteristics. The converted tensile films are particularly advantageous as work function adjusting films in PMOS transistor devices and are advantageously used in conjunction with additional metal gate materials. | 02-14-2013 |
20130102142 | STRESS MODULATION FOR METAL GATE SEMICONDUCTOR DEVICE - The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon. | 04-25-2013 |
20140197455 | SEMICONDUCTOR SUBSTRUCTURE HAVING ELEVATED STRAIN MATERIAL-SIDEWALL INTERFACE AND METHOD OF MAKING THE SAME - A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate. | 07-17-2014 |
20140291777 | BUFFER LAYER ON SEMICONDUCTOR DEVICES - A semiconductor device including a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region. Additionally, the semiconductor device includes a high-k dielectric layer formed over the channel region, an n-metal formed over the high-k dielectric layer and a barrier layer formed between the high-k dielectric layer and the n-metal, the barrier layer including a layer of annealed silicon. | 10-02-2014 |
Patent application number | Description | Published |
20130071967 | Method for Making a Nickel Film for Use as an Electrode of an N-P Diode or Solar Cell - Disclosed is a method for making a nickel film for use as an electrode of an n-p diode or solar cell. A light source is used to irradiate an n-type surface of the n-p diode or solar cell, thus producing electron-hole pairs in the n-p diode or solar cell. For the electric field effect at an n-p interface, electrons drift to and therefore accumulate on the n-type surface. With a plating agent, the diode voltage is added to the chemical potential for electroless plating of nickel on the n-type surface. The nickel film can be used as a buffer layer between a contact electrode and the diode or solar cell. The nickel film reduces the contact resistance to prevent a reduced efficiency of the diode or solar cell that would otherwise be caused by diffusion of the atoms of the electrode in following electroplating. | 03-21-2013 |
20140034110 | PHOTOVOLTAIC SYSTEM ABLE TO FLOAT ON WATER AND TRACK SUN - A photovoltaic system able to float on water and track sun includes a floating mechanism; an adjusting mechanism, combining with the floating mechanism; and a solar power mechanism, combining with the adjusting mechanism and located above the floating mechanism. This photovoltaic system can be located on the water surface, and has its floating mechanism to be under water by using the adjusting mechanism and the surrounding water source. The adjusting mechanism can be further used to adjust the solar power mechanism to a specific tilt angle according to the water level of the surrounding water and the sun-tracking angles that varies as the locations of the sun. Therefore, a novel photovoltaic system with simplified configuration, accurate sun tracking and enhanced power generation efficiency can be achieved. | 02-06-2014 |
20140110264 | LIGHT INDUCED NICKEL PLATING METHOD FOR P-TYPE SILICON AND N/P SOLAR CELL MATERIAL - A simple and fast light induced nickel plating method for p-type silicon wafer and n/p silicon solar cell material is revealed. When a n/p solar cell or p-Si semiconductor substrate, which is subjected to metallization with metal contact on the rear side, is immersed in a plating bath, metal ions are reduced on the front surface of semiconductor as soon as illumination starts on the front. The mechanism of nickel plating in this invention is nickel electroplating under the reduction reaction with the use of interfacial potential between the nickel plating bath and the metal surface. It does not need any surface catalytic processing and extra voltage. Instead, it can carry out the nickel deposition on the specific surface with a high nickel plating rate, a simple process and a low production cost. | 04-24-2014 |