Patent application number | Description | Published |
20130126980 | SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES HAVING CONDUCTIVE CONTACTS POSITIONED THEREBETWEEN - Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures. | 05-23-2013 |
20130137257 | Method of Forming a Semiconductor Device by Using Sacrificial Gate Electrodes and Sacrificial Self-Aligned Contact Structures - Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure. | 05-30-2013 |
20130181299 | Strain Engineering in Three-Dimensional Transistors Based on Strained Isolation Material - In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors. | 07-18-2013 |
20140027825 | THRESHOLD VOLTAGE ADJUSTMENT IN A FIN TRANSISTOR BY CORNER IMPLANTATION - When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins. | 01-30-2014 |
20140077308 | ENCAPSULATION OF CLOSELY SPACED GATE ELECTRODE STRUCTURES - A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material. | 03-20-2014 |
20140134822 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SEMICONDUCTIVE RESISTOR STRUCTURES IN A FINFET ARCHITECTURE - A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers. | 05-15-2014 |
20140220759 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS - Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect. | 08-07-2014 |
20150021695 | EPITAXIAL BLOCK LAYER FOR A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate. | 01-22-2015 |
20150050792 | EXTRA NARROW DIFFUSION BREAK FOR 3D FINFET TECHNOLOGIES - Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench. | 02-19-2015 |
20150076653 | OVERLAY PERFORMANCE FOR A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification. | 03-19-2015 |
20150091093 | INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME - Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal. | 04-02-2015 |
20150091094 | DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION - Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate. | 04-02-2015 |
20150104918 | FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS - Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges. | 04-16-2015 |
20150115418 | DEVICES AND METHODS OF FORMING FINS AT TIGHT FIN PITCHES - Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer. | 04-30-2015 |
20150123211 | NARROW DIFFUSION BREAK FOR A FIN FIELD EFFECT (FinFET) TRANSISTOR DEVICE - Approaches for providing a narrow diffusion break in a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device is provided with a set of fins formed from a substrate, and an opening formed through the set of fins, the opening oriented substantially perpendicular to an orientation of the set of fins. This provides a FinFET device capable of achieving cross-the-fins insulation with an opening size that is adjustable from approximately 20-30 nm. | 05-07-2015 |
20150132962 | FACILITATING MASK PATTERN FORMATION - Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern. | 05-14-2015 |
20150137194 | INVERTED CONTACT AND METHODS OF FABRICATION - An inverted contact and methods of fabrication are provided. A sacrificial layer is patterned in an inverted trapezoid shape, and oxide is deposited around the pattern. The sacrificial layer is removed, and a metal contact material is deposited, taking an inverted-trapezoid shape. Embodiments of the present invention provide an inverted contact, having a wider base and a narrower top. The wider base provides improved electrical contact to the underlying active area. The narrower top allows for closer placement of adjacent contacts, serving to increase overall circuit density of an integrated circuit. | 05-21-2015 |
20150194419 | THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE - Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current. | 07-09-2015 |
20150214113 | METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS - A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings. | 07-30-2015 |
20150214330 | REPLACEMENT LOW-K SPACER - A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer. | 07-30-2015 |
20150228649 | TRANSISTOR WITH WELL TAP IMPLANT - A fin of a FinFET, being p or n-type, includes a well encompassing the active region, the well being of the opposite type than the fin. An implant of the same type as the well is provided for the well tap at an edge of the active region. A dummy gate material on the fin between the source/drain and the well tap implant reduces an inherent resistance of a well tap contact. | 08-13-2015 |
20150228755 | INTEGRATED CIRCUITS WITH RELAXED SILICON / GERMANIUM FINS - Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively. | 08-13-2015 |
20150236133 | DEVICES AND METHODS OF FORMING HIGHER TUNABILITY FINFET VARACTOR - Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels. | 08-20-2015 |
20150263089 | NON-PLANAR SEMICONDUCTOR DEVICE WITH P-N JUNCTION LOCATED IN SUBSTRATE - A non-planar diode is fabricated, with an n- or p-type raised structure, such as a fin, coupled to the substrate. A well of an opposite type is located under the raised structure, along with an area having additional impurity, located directly under the raised structure, and within the well. This additional implant creates a p-n junction within the substrate, the non-planar diode having an ideality factor in a range of 1 to about 1.05. | 09-17-2015 |
20150287595 | DEVICES AND METHODS OF FORMING FINS AT TIGHT FIN PITCHES - Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer. | 10-08-2015 |
20150325473 | INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS - Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device. | 11-12-2015 |
20150333067 | DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION - Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate. | 11-19-2015 |
20160049489 | INTEGRATED CIRCUITS WITH NANOWIRES AND METHODS OF MANUFACTURING THE SAME - Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain. | 02-18-2016 |
20160049490 | INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME - Integrated circuits with dual silicide contacts are provided. In an embodiment, an integrated circuit includes a semiconductor substrate including a first area and a second area. The integrated circuit includes a first source/drain region in and/or overlying the first area of the semiconductor substrate and a second source/drain region in and/or overlying the second area of the semiconductor substrate. The integrated circuit further includes a first contact over the first source/drain region and comprising a first metal silicide. The integrated circuit also includes a second contact over the second source/drain region and comprising a second metal silicide different from the first metal silicide. | 02-18-2016 |
20160064372 | ESD SNAPBACK BASED CLAMP FOR FINFET - There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate. | 03-03-2016 |
20160079242 | PATTERNING MULTIPLE, DENSE FEATURES IN A SEMICONDUCTOR DEVICE USING A MEMORIZATION LAYER - Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures. | 03-17-2016 |
Patent application number | Description | Published |
20130309838 | METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS ON BULK SEMICONDUCTOR SUBSTRATES - Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins. | 11-21-2013 |
20130328112 | SEMICONDUCTOR DEVICES HAVING IMPROVED GATE HEIGHT UNIFORMITY AND METHODS FOR FABRICATING SAME - Semiconductor devices and methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming on a semiconductor surface a temporary gate structure including a polysilicon gate and a cap. A spacer is formed around the temporary gate structure. The cap and a portion of the spacer are removed. A uniform liner is deposited overlying the polysilicon gate. The method removes a portion of the uniform liner overlying the polysilicon gate and the polysilicon gate to form a gate trench. Then, a replacement metal gate is formed in the gate trench. | 12-12-2013 |
20140004692 | FINFET STRUCTURE WITH MULTIPLE WORKFUNCTIONS AND METHOD FOR FABRICATING THE SAME | 01-02-2014 |
20140038402 | DUAL WORK FUNCTION FINFET STRUCTURES AND METHODS FOR FABRICATING THE SAME - A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer. | 02-06-2014 |
20140131831 | INTEGRATED CIRUIT INCLUDING AN FIN-BASED DIODE AND METHODS OF ITS FABRICATION - A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin. | 05-15-2014 |
20140159126 | METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS - One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material. | 06-12-2014 |
20140264631 | METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES AND THE RESULTING ALIGNMENT/OVERLAY MARK - One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate. | 09-18-2014 |
20140273365 | METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES BY FORMING A REGION THAT INCLUDES A SCHOTTKY BARRIER LOWERING MATERIAL - Various methods of forming conductive contacts to the source/drain regions of FinFET devices that involves forming a region comprised of a Schottkky barrier lowering material are disclosed. The method disclosed herein includes forming at least one fin for an N-type FinFET device (or a P-type FinFET device) in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a Schottky barrier lowering material, depositing a layer of a valence band metal (for an N-type device) or a conduction band metal (for a P-type device) on the region and forming a metal silicide region on the fin, wherein the metal silicide is comprised of the valance band metal (for the N-type device) or a conduction band metal (for the P-type device). | 09-18-2014 |
20140273369 | METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES - In one example, the method disclosed herein includes forming at least one fin for a FinFET device in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a metal diffusion inhibiting material, depositing a layer of metal on the region in the at least one fin and forming a metal silicide region on the at least one fin. | 09-18-2014 |
20140273429 | METHODS OF FORMING FINFET DEVICES WITH A SHARED GATE STRUCTURE - In one example, the method disclosed herein includes forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, wherein the second type is opposite to the first type, and forming a first sidewall spacer around an entire perimeter of the sacrificial gate structure in a single process operation. | 09-18-2014 |
20150123214 | METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS - A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures. | 05-07-2015 |
20150214059 | INTEGRATED CIRCUITS WITH METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACT STRUCTURES AND METHODS FOR FABRICATING SAME - Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure. | 07-30-2015 |
20150214228 | IINTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME - Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions. | 07-30-2015 |
20150279971 | METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS - One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining initial fins, with the fin protection layer in position, performing an etching process to extend a depth of the first trenches to thereby define a plurality of final trenches with a final trench depth, wherein the final trenches define a plurality of final fin structures that each comprise an initial fin, removing the fin protection layer, and forming a recessed layer of insulating material in the final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of the final fin structures. | 10-01-2015 |
20150279999 | FINFET DEVICES WITH DIFFERENT FIN HEIGHTS IN THE CHANNEL AND SOURCE/DRAIN REGIONS - One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity. | 10-01-2015 |
20150311081 | METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES - One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode. | 10-29-2015 |
20150333162 | METHODS OF FORMING NANOWIRE DEVICES WITH METAL-INSULATOR-SEMICONDUCTOR SOURCE/DRAIN CONTACTS AND THE RESULTING DEVICES - A device includes a gate structure and a nanowire channel structure positioned under the gate structure. The nanowire channel structure includes first and second end surfaces. The device further includes a first insulating liner positioned on the first end surface and a second insulating liner positioned on the second end surface. The device further includes a metal-containing source contact positioned on the first insulating liner and a metal-containing drain contact positioned on the second insulating liner. | 11-19-2015 |
20150372111 | METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES - A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers. | 12-24-2015 |
20150372115 | METHODS OF FORMING NANOWIRE DEVICES WITH DOPED EXTENSION REGIONS AND THE RESULTING DEVICES - A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device. | 12-24-2015 |
20150372139 | CONSTRAINING EPITAXIAL GROWTH ON FINS OF A FINFET DEVICE - A method includes forming at least one fin in a semiconductor substrate, forming a fin spacer on at least a first portion of the fin, the fin spacer having an upper surface, recessing the at least one fin to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer, and forming a first epitaxial material on the recessed fin, wherein a lateral extension of the epitaxial material is constrained by the fin spacer. | 12-24-2015 |
20160093713 | SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES - A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material. | 03-31-2016 |
Patent application number | Description | Published |
20150214345 | DOPANT DIFFUSION BARRIER TO FORM ISOLATED SOURCE/DRAINS IN A SEMICONDUCTOR DEVICE - Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain. | 07-30-2015 |
20150236106 | METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS - Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips. | 08-20-2015 |
20150270175 | PARTIALLY CRYSTALLIZED FIN HARD MASK FOR FIN FIELD-EFFECT-TRANSISTOR (FINFET) DEVICE - Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements. | 09-24-2015 |
20150270400 | SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS - Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device). | 09-24-2015 |
20150279684 | METHOD OF FORMING SEMICONDUCTOR FINS - Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed. | 10-01-2015 |
20150287636 | TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS - Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them. | 10-08-2015 |
20150303273 | PATTERNING MULTIPLE, DENSE FEATURES IN A SEMICONDUCTOR DEVICE USING A MEMORIZATION LAYER - Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures. | 10-22-2015 |
20150303295 | SELF-ALIGNED CONTACT OPENINGS OVER FINS OF A SEMICONDUCTOR DEVICE - Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings. | 10-22-2015 |
20150311082 | SELF-ALIGNED GATE CONTACT FORMATION - Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch. | 10-29-2015 |
20150311199 | MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE - Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density. | 10-29-2015 |
20150340461 | METAL GATE STRUCTURE AND METHOD OF FORMATION - Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures. | 11-26-2015 |
20150340467 | MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE - Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged. | 11-26-2015 |
20150380250 | SEMICONDUCTOR CONTACTS AND METHODS OF FABRICATION - Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts. | 12-31-2015 |
20160005868 | FINFET WITH CONFINED EPITAXY - Embodiments of the present invention provide a fin-type field effect transistor (finFET) with confined epitaxy. A protective layer is formed on a fin. The protective layer is recessed to expose the fin top. A fin cavity is formed in the fin. An epitaxial region is formed in the fin cavity. The epitaxial region has a confined portion and a diamond-shaped portion, resulting in increased epitaxial volume. The increased epitaxial volume can result in enhanced carrier mobility and improved device performance. | 01-07-2016 |
20160043081 | METHOD OF FORMING SEMICONDUCTOR FINS - Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed. | 02-11-2016 |
20160049481 | TRANSISTOR CONTACTS SELF-ALIGNED TWO DIMENSIONS - Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them. | 02-18-2016 |
20160056075 | PRECUT METAL LINES - Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided. | 02-25-2016 |
20160056104 | SELF-ALIGNED BACK END OF LINE CUT - Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density. | 02-25-2016 |
20160064514 | BORDERLESS CONTACT FORMATION THROUGH METAL-RECESS DUAL CAP INTEGRATION - An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s). | 03-03-2016 |
20160071774 | OPPOSITE POLARITY BORDERLESS REPLACEMENT METAL CONTACT SCHEME - An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer. | 03-10-2016 |
20160093704 | METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS - Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips. | 03-31-2016 |
20160118341 | PRECUT METAL LINES - Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided. | 04-28-2016 |
Patent application number | Description | Published |
20090307106 | PERFORMING AUTOMATICALLY AUTHORIZED PROGRAMMATIC TRANSACTIONS - Techniques are described for facilitating interactions between computing systems, such as by performing transactions between parties that are automatically authorized via a third-party transaction authorization system. In some situations, the transactions are programmatic transactions involving the use of fee-based Web services by executing application programs, with the transaction authorization system authorizing and/or providing payments in accordance with private authorization instructions previously specified by the parties. The authorization instructions may include predefined instruction rule sets that regulate conditions under which a potential transaction can be authorized, with the instruction rule sets each referenced by an associated reference token. After one or more of the parties to a potential transaction supply reference tokens for the parties, the transaction authorization system can determine whether to authorize the transaction based on whether the instruction rule sets associated with the reference tokens are compatible or otherwise satisfied. | 12-10-2009 |
20090307107 | PERFORMING AUTOMATICALLY AUTHORIZED PROGRAMMATIC TRANSACTIONS - Techniques are described for facilitating interactions between computing systems, such as by performing transactions between parties that are automatically authorized via a third-party transaction authorization system. In some situations, the transactions are programmatic transactions involving the use of fee-based Web services by executing application programs, with the transaction authorization system authorizing and/or providing payments in accordance with private authorization instructions previously specified by the parties. The authorization instructions may include predefined instruction rule sets that regulate conditions under which a potential transaction can be authorized, with the instruction rule sets each referenced by an associated reference token. After one or more of the parties to a potential transaction supply reference tokens for the parties, the transaction authorization system can determine whether to authorize the transaction based on whether the instruction rule sets associated with the reference tokens are compatible or otherwise satisfied. | 12-10-2009 |
20090307134 | PERFORMING AUTOMATICALLY AUTHORIZED PROGRAMMATIC TRANSACTIONS - Techniques are described for facilitating interactions between computing systems, such as by performing transactions between parties that are automatically authorized via a third-party transaction authorization system. In some situations, the transactions are programmatic transactions involving the use of fee-based Web services by executing application programs, with the transaction authorization system authorizing and/or providing payments in accordance with private authorization instructions previously specified by the parties. The authorization instructions may include predefined instruction rule sets that regulate conditions under which a potential transaction can be authorized, with the instruction rule sets each referenced by an associated reference token. After one or more of the parties to a potential transaction supply reference tokens for the parties, the transaction authorization system can determine whether to authorize the transaction based on whether the instruction rule sets associated with the reference tokens are compatible or otherwise satisfied. | 12-10-2009 |
20090307135 | PERFORMING AUTOMATICALLY AUTHORIZED PROGRAMMATIC TRANSACTIONS - Techniques are described for facilitating interactions between computing systems, such as by performing transactions between parties that are automatically authorized via a third-party transaction authorization system. In some situations, the transactions are programmatic transactions involving the use of fee-based Web services by executing application programs, with the transaction authorization system authorizing and/or providing payments in accordance with private authorization instructions previously specified by the parties. The authorization instructions may include predefined instruction rule sets that regulate conditions under which a potential transaction can be authorized, with the instruction rule sets each referenced by an associated reference token. After one or more of the parties to a potential transaction supply reference tokens for the parties, the transaction authorization system can determine whether to authorize the transaction based on whether the instruction rule sets associated with the reference tokens are compatible or otherwise satisfied. | 12-10-2009 |
20120296827 | PERFORMING AUTOMATICALLY AUTHORIZED PROGRAMMATIC TRANSACTIONS - Techniques are described for facilitating interactions between computing systems, such as by performing transactions between parties that are automatically authorized via a third-party transaction authorization system. In some situations, the transactions are programmatic transactions involving the use of fee-based Web services by executing application programs, with the transaction authorization system authorizing and/or providing payments in accordance with private authorization instructions previously specified by the parties. The authorization instructions may include predefined instruction rule sets that regulate conditions under which a potential transaction can be authorized, with the instruction rule sets each referenced by an associated reference token. After one or more of the parties to a potential transaction supply reference tokens for the parties, the transaction authorization system can determine whether to authorize the transaction based on whether the instruction rule sets associated with the reference tokens are compatible or otherwise satisfied. | 11-22-2012 |
20130238504 | PERFORMING AUTOMATICALLY AUTHORIZED PROGRAMMATIC TRANSACTIONS - Techniques are described for facilitating interactions between computing systems, such as by performing transactions between parties that are automatically authorized via a third-party transaction authorization system. In some situations, the transactions are programmatic transactions involving the use of fee-based Web services by executing application programs, with the transaction authorization system authorizing and/or providing payments in accordance with private authorization instructions previously specified by the parties. The authorization instructions may include predefined instruction rule sets that regulate conditions under which a potential transaction can be authorized, with the instruction rule sets each referenced by an associated reference token. After one or more of the parties to a potential transaction supply reference tokens for the parties, the transaction authorization system can determine whether to authorize the transaction based on whether the instruction rule sets associated with the reference tokens are compatible or otherwise satisfied. | 09-12-2013 |
Patent application number | Description | Published |
20090029615 | Crystallizable Polyetherimides, Method of Manufacture, and Articles Derived Therefrom - A composition is described, which comprises a crystallizable polyetherimide derived from the polymerization of: (a) a dianhydride component, comprising more than 96.8 mole % of 4,4′-bisphenol A dianhydride or a chemical equivalent thereof; and (b) a diamine component comprising a diamine or a chemical equivalent thereof, wherein the crystallizable polyetherimide has a T | 01-29-2009 |
20090061713 | ARTICLE AND ASSOCIATED METHOD - An article includes a reaction product of a filler having binding sites, a coupling agent composition including an aromatic amine and a first cycloolefin substituted with at least one epoxy group, a polymer precursor including a second cycloolefin, and a metathesis catalyst capable of catalyzing a ring-opening metathesis polymerization reaction when contacted to the first cycloolefin or the second cycloolefin. The coupling agent composition is capable of bonding to the filler and the coupling agent composition is compatible with a metathesis catalyst. An associated method is also provided. | 03-05-2009 |
20090062441 | COMPOSITION AND ASSOCIATED METHOD - A composition includes a coupling agent composition and a polymer precursor. The coupling agent composition includes an aromatic amine and a first cycloolefin substituted with at least one epoxy group. The polymer precursor includes a second cycloolefin. The coupling agent composition is capable of bonding to a filler having a corresponding binding site and the coupling agent composition is compatible with a metathesis catalyst capable of catalyzing a ring-opening metathesis polymerization reaction when contacted to the first cycloolefin or the second cycloolefin. An associated method is also provided. | 03-05-2009 |
20090062442 | COMPOSITION AND ASSOCIATED METHOD - A composition includes a first cycloolefin substituted with at least one epoxy group and an aromatic amine. The composition is capable of bonding to a filler having a corresponding binding site. The composition is compatible with a metathesis catalyst capable of catalyzing a ring-opening metathesis polymerization reaction when contacted to the first cycloolefin. An associated method is also provided. | 03-05-2009 |
20090062446 | COMPOSITION AND ASSOCIATED METHOD - A composition includes a coupling agent composition and a polymer precursor. The coupling agent composition includes an aromatic amine and a first cycloolefin substituted with at least one epoxy group. The polymer precursor includes a second cycloolefin and an epoxy compound. The coupling agent composition is capable of bonding to a filler having a corresponding binding site and the coupling agent composition is compatible with a metathesis catalyst capable of catalyzing a ring-opening metathesis polymerization reaction when contacted to the first cycloolefin or the second cycloolefin. An associated method is also provided. | 03-05-2009 |
20090143510 | COMPOSITION, ARTICLE, AND ASSOCIATED METHOD - A composition includes a polymer precursor and a coupling agent composition capable of bonding to a filler having a corresponding binding site. The polymer precursor includes cycloolefin and the coupling agent has at least one functional group that is an epoxy, an amine, an imine, a thiol, a carboxylic acid, a cyanato, a carboxylic acid anhydride, a cyano group, or a silane group. A method to make the composition is also provided. | 06-04-2009 |
20100148903 | ELECTRICAL ENERGY TRANSFORMATION APPARATUS - In one aspect, the present invention provides a high voltage-high frequency electrical energy transformation apparatus comprising a frequency inverter capable of converting 60 Hz electrical energy into 40-100 KHz electrical energy; and a voltage transformer. The voltage transformer comprises a transformer housing; at least one soft magnetic core; a low voltage primary winding and a high voltage secondary winding; and a solid insulating material comprising polydicyclopentadiene. The solid insulating material is in contact with the high voltage secondary winding. | 06-17-2010 |
20150337461 | Crystallizable Polyetherimides, Method of Manufacture, and Articles Derived Therefrom - A composition is described, which comprises a crystallizable polyetherimide derived from the polymerization of: (a) a dianhydride component, comprising more than 96.8 mole % of 4,4′-bisphenol A dianhydride or a chemical equivalent thereof; and (b) a diamine component comprising a diamine or a chemical equivalent thereof, wherein the crystallizable polyetherimide has a T | 11-26-2015 |
Patent application number | Description | Published |
20100151365 | Patterning Methods and Masks - Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width. | 06-17-2010 |
20110133304 | Structure and Method for Placement, Sizing and Shaping of Dummy Structures - A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas. | 06-09-2011 |
20120282774 | Patterning Methods and Masks - Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width. | 11-08-2012 |
20130267048 | Structure and Method for Placement, Sizing and Shaping of Dummy Structures - A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas. | 10-10-2013 |
20140113420 | METHODS OF AVOIDING SHADOWING WHEN FORMING SOURCE/DRAIN IMPLANT REGIONS ON 3D SEMICONDUCTOR DEVICES - One illustrative method disclosed herein includes forming a patterned photoresist implant mask that has an opening that is defined, at least partially, by a plurality of non-vertical sidewalls, wherein the implant mask covers one of an N-type FinFET or P-type FinFET device, while the other of the N-type FinFET or P-type FinFET device is exposed by the opening in the patterned photoresist implant mask, and performing at least one source/drain implant process through the opening in the patterned photoresist implant mask to form a doped source/drain implant region in at least one fin of the FinFET device exposed by the opening in the patterned photoresist implant mask. | 04-24-2014 |
20140211175 | ENHANCING RESOLUTION IN LITHOGRAPHIC PROCESSES USING HIGH REFRACTIVE INDEX FLUIDS - An approach for enhancing resolution in a lithographic process (e.g., an immersion lithographic process) is provided. Specifically, a material having a high reflexive index (e.g., water) is provided on opposite sides of an objective lens. This allows a set of light rays (high intensity) to be directed/passed from a light source, through a condenser lens, over a mask, through the material positioned on one side of the objective lens, through the objective lens, through the material on the opposite side of the objective lens, and to a wafer that is then patterned. Positioning the material on both sides of the objective lens allows for improved resolution and lithographic patterning of the wafer for both on-axis illumination and off-axis illumination techniques. | 07-31-2014 |
20140246605 | DEFECT REMOVAL PROCESS - A process is provided for the removal of defects, for example, micro-bridging defects during device fabrication. In one aspect, a method includes: obtaining a wafer after lithography processing and exposing the wafer to at least one electron beam. In another aspect, a system includes: selecting a substrate with micro-bridging defects after the substrate undergoes lithography processing; preparing the substrate for exposure to at least one electron beam; and exposing the substrate to the at least one electron beam. | 09-04-2014 |
Patent application number | Description | Published |
20080220524 | Three dimensional gum matrices for cell culture, manufacturing methods and methods of use - This invention relates three dimensional porous cell culture matrices or scaffolds which have directional porous structure. More particularly, this invention relates to three dimensional porous cell culture matrices or scaffolds for cell culture which are derived from or contain gums including naturally occurring gums, plant gums, galactomannan gums or derivatives thereof. The invention also relates to methods of making the matrices, articles of manufacture (e.g., cell culture vessels and labware) having such matrices or scaffolds, methods of applying these materials to cell culture surfaces, and methods of using cell culture vessels having these three dimensional porous cell culture matrices or scaffolds. | 09-11-2008 |
20080220526 | Gum coatings for cell culture, methods of manufacture and methods of use - This invention relates to coatings for cell culture surfaces. More particularly, this invention relates to coatings for cell culture surfaces which are derived from or contain gums including naturally occurring gums, plant gums, galactomannan gums or derivatives thereof. The invention also relates to articles of manufacture (e.g., cell culture vessels and labware) having such coatings, methods of applying these coatings to cell culture surfaces, and methods of using coated cell culture vessel. | 09-11-2008 |
20100129854 | LIVER CELL TOXICITY ASSAY - The disclosure provides methods for characterizing the toxicity of a candidate molecule to liver cells as defined herein; methods of culturing metabolically active liver cells on a biosensor as defined herein; and biosensor liver culture systems as defined herein. | 05-27-2010 |
20100129908 | SPACED PROJECTION SUBSTRATES AND DEVICES FOR CELL CULTURE - An article for culturing cells includes a substrate on which cells can be cultured. The substrate has a base surface. An array of projections extends from the base surface. The projections have a height of about 1 micrometer to about 100 micrometers, and have a gap distance along the major surface from center to center between neighboring projections of about 10 micrometers to 80 micrometers. A plurality of arrays of projections may extend from the surface with gaps in the base surface between the arrays. Hepatocytes cultures on such microprojection array substrates maintained in vivo like morphology and membrane polarity. Hepatocytes co-cultured with helper cells on such substrates tended to grow in the area of the arrays, while the helper cells tended to grow in the areas between the arrays. | 05-27-2010 |
20110246078 | MITOCHONDRIA KATP ION CHANNEL AS A DRUG TARGET FOR PREVENTING LIVER DISEASES AND METHODS TO SCREEN MITOCHONDRIA KATP MODULATORS - Disclosed are compositions and methods related to modulation of K | 10-06-2011 |
20120034435 | COATED, ANTIMICROBIAL, CHEMICALLY STRENGTHENED GLASS AND METHOD OF MAKING - The disclosure is directed to a chemically strengthened glass having antimicrobial properties and to a method of making such glass. In particular, the disclosure is directed to a chemically strengthened glass with antimicrobial properties and with a low surface energy coating on the glass that does not interfere with the antimicrobial properties of the glass. The antimicrobial has an Ag ion concentration on the surface in the range of greater than zero to 0.047 μg/cm | 02-09-2012 |
20120295965 | FUSED THIOPHENES AS DUAL INHIBITORS OF EGFR/VEGFR AND THEIR USE IN THE TREATMENT OF CANCER - Disclosed are compositions and methods related to identification of modulators of EGFR and VEGFR. | 11-22-2012 |
20120329865 | MOLECULES RELATED hERG ION CHANNELS AND THE USE THEREOF - Disclosed are compounds having structural formula (I, II) or a pharmaceutically acceptable sale, solvate, clathrate, or prodrug thereof, wherein R | 12-27-2012 |
20140017462 | ANTIMICROBIAL ACTION OF Cu, CuO and Cu20 NANOPARTICLES ON GLASS SURFACES AND DURABLE COATINGS - A transparent cover glass for applications such as, but not limited to, touch screen devices that embody antimicrobial properties that include s being antibacterial, antifungal, and antiviral. The antimicrobial glasses contain nanoparticles of Cu or Cu | 01-16-2014 |
20140072783 | COATED, ANTIMICROBIAL, CHEMICALLY STRENGTHENED GLASS AND METHOD OF MAKING - The disclosure is directed to a chemically strengthened glass having antimicrobial properties and to a method of making such glass. In particular, the disclosure is directed to a chemically strengthened glass with antimicrobial properties and with a low surface energy coating on the glass that does not interfere with the antimicrobial properties of the glass. The antimicrobial has an Ag ion concentration on the surface in the range of greater than zero to 0.047 μg/cm | 03-13-2014 |
20140079807 | ANTIMICROBIAL ACTION OF COPPER IN GLASS - The disclosure is directed to glass compositions that incorporate copper into an otherwise homogeneous glass and to a method for making such glass. This incorporation of the copper into the glass composition imparts significant antimicrobial activity to the glass. A method of making a copper-containing glass article comprises: batching a glass batch comprising: 40-85 SiO | 03-20-2014 |
20140105953 | ANTIMICROBIAL GLASS-CERAMICS - The application discloses the formation of antimicrobial glass-ceramic articles having an amorphous phase and a crystalline phase and an antimicrobial agent selected from the group consisting of silver, copper and a mixture of silver and copper. The antimicrobial glass-ceramic can have a Log Reduction of >2. | 04-17-2014 |
20140212467 | Antimicrobial Composite Material - The present disclosure is directed to an antimicrobial composite material, and more particularly to an antimicrobial composite material comprising particles having a metal or metal alloy core and a porous inorganic material shell, coatings including the antimicrobial composite material, and methods of making the same. In some embodiments, Cu—SiO | 07-31-2014 |
20140322547 | Antimicrobial Glass Articles and Methods for Making and Using Same - Described herein are coated glass or glass-ceramic articles having improved antimicrobial efficacy. Further described are methods of making and using the improved articles. The coated articles generally include a glass or glass-ceramic substrate and an antimicrobial coating disposed thereon. The antimicrobial coating is not a free-standing adhesive film, but a coating that is formed on or over at least a portion of a surface of the glass or glass-ceramic substrate. | 10-30-2014 |
20140370066 | Antimicrobial Glass-Ceramics - The application discloses the formation of antimicrobial glass-ceramic articles having an amorphous phase and a crystalline phase and an antimicrobial agent selected from the group consisting of silver, copper and a mixture of silver and copper. The antimicrobial glass-ceramic can have a Log Reduction of >2. | 12-18-2014 |
20150118276 | COATED, ANTIMICROBIAL, CHEMICALLY STRENGTHENED GLASS AND METHOD OF MAKING - The disclosure is directed to a chemically strengthened glass having antimicrobial properties and to a method of making such glass. In particular, the disclosure is directed to a chemically strengthened glass with antimicrobial properties and with a low surface energy coating on the glass that does not interfere with the antimicrobial properties of the glass. The antimicrobial has an Ag ion concentration on the surface in the range of greater than zero to 0.047 μg/cm | 04-30-2015 |
20150147775 | TEST METHOD FOR EFFICACY OF SILVER SURFACES AS A SANITIZER - A method that includes the steps: inoculating nutrient agar with bacterial stock to form a culture; incubating the culture to form a first incubated culture; incubating a portion of the first culture with nutrient agar to form a second culture; incubating a portion of the second culture to form a third culture; incubating the third culture to form an inoculated test plate; forming an inoculum by suspending bacteria from the inoculated test plate in a buffered test solution, adjusting the pH to ˜7 to 8, and adding organic soil at a concentration of approximately 10% to 30% by weight; inoculating a silver-containing surface region of a test carrier with a portion of the inoculum; incubating the inoculated test carrier; washing the test carrier in a neutralizing solution to form a residual test inoculum; and calculating the percent reduction in the number of surviving bacterial colonies in the residual test inoculum. | 05-28-2015 |
20150208664 | ANTIMICROBIAL ACTION OF Cu, CuO and Cu2O NANOPARTICLES ON GLASS SURFACES AND DURABLE COATINGS - A transparent cover glass for applications such as, but not limited to, touch screen devices that embody antimicrobial properties that include s being antibacterial, antifungal, and antiviral. The antimicrobial glasses contain nanoparticles of Cu or Cu | 07-30-2015 |
20150367270 | ANTI-MICROBIAL AIR FILTER - An air filter article, including:
| 12-24-2015 |