Patent application number | Description | Published |
20090289345 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes. | 11-26-2009 |
20100289092 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 11-18-2010 |
20110042819 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer. | 02-24-2011 |
20110084382 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed. | 04-14-2011 |
20110193225 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 08-11-2011 |
20130045571 | METHOD FOR FABRICATING ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 02-21-2013 |
20130062759 | ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 03-14-2013 |
20130193520 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 08-01-2013 |
20130312813 | SOLAR CELL AND MODULE THEREOF - A solar cell includes a silicon semiconductor substrate, a composite multifunctional protective film, a plurality of front electrodes and a plurality of back electrodes. The silicon semiconductor substrate has a roughened first surface. A depth of the doped layer arranged under the first surface ranges from 200 nm to 1000 nm. A surface doping concentration of the doped layer ranges from 1×10 | 11-28-2013 |
20140251422 | SOLAR CELL WITH DOPING BLOCKS - A solar cell with doping blocks is provided, which includes: a semiconductor substrate, an anti-reflection layer, a plurality of front electrodes, and a back electrode layer. The semiconductor substrate has a first surface, and a plurality of doping block layers is arranged under the first surface and spaced from each other. The anti-reflection layer is disposed on the doping block layer and the semiconductor substrate. The front electrodes penetrate the anti-reflection layer and are arranged on the doping block layers. The back electrode layer is disposed on a second surface of the semiconductor substrate. | 09-11-2014 |
20140284792 | ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 09-25-2014 |
20140352773 | SOLAR CELL - A solar cell includes a photovoltaic substrate having a first surface and a second surface and a plurality of bus bar electrode net structures. The bus bar electrode net structures are separately disposed on the first surface, each bus bar electrode net structure includes a bus bar electrode, a plurality of finger electrodes, at least one connecting line electrode and at least one vertical finger electrode. The bus bar electrode is disposed on the first surface. The finger electrodes are separately disposed at two sides of the bus bar electrode. The connecting line electrode is disposed on the first surface. Each connecting line electrode connects with ends of at least two finger electrodes. The vertical finger electrode is disposed on the first surface, and is parallel to the bus bar electrode and disposed between the two ends of the finger electrode to connect with at least two adjacent finger electrodes. | 12-04-2014 |
20140366937 | SOLAR CELL - A solar cell is disclosed, which includes: a semiconductor substrate, an anti-reflective layer, a passivation layer, a back electrode and back bus bar. The semiconductor substrate has a first surface and a second surface. The anti-reflective layer is disposed on the first surface. The back electrode is a continuous electrode or a flat electrode overlapping the whole back side of the solar cell. The continuous electrode or the flat electrode connects to the semiconductor substrate through a continuous opening. In another embodiment, the continuous electrode is passing through the passivation layer directly and connecting to the semiconductor substrate. That is, the solar cell includes a continuous opening or a continuous electrode. | 12-18-2014 |