Wang, Tainan
Bill Wang, Tainan TW
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20130229021 | Durable Cylindrical Lock - A cylindrical lock includes a retractor ( | 09-05-2013 |
Chen-Yu Wang, Tainan TW
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20110128047 | HALF-POWER BUFFER AMPLIFIER - A half-power buffer amplifier includes a buffer stage having a first-half buffer stage and a second-half buffer stage. An output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. A switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. | 06-02-2011 |
20110260758 | HALF-POWER BUFFER AMPLIFIER - A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground. | 10-27-2011 |
Chien-Kang Wang, Tainan TW
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20150239106 | RATCHET CONNECTOR - A ratchet connector may include a first body, a ratchet, a control ring and a second body. The first body has a cylinder at one end and a semi-circular trough formed at an outer surface of the cylinder and a through hole at the semi-circular trough. The ratchet has a teeth portion on both sides of an arc surface thereof, a sliding surface formed between two teeth portions, a shaft rod configured to be insert into the through hole to enable the ratchet to be pivotally disposed in the semi-circular trough. The control ring having a fixed trough and a switching trough and the control ring disposed onto the cylinder of the first body to enable the switching trough to be disposed against the ball; and the second body having a receiving space and a ring teeth portion is formed inside the receiving space. | 08-27-2015 |
Chih-Hung Wang, Tainan TW
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20120141989 | KIT AND METHOD FOR RAPIDLY DETECTING A TARGET NUCLEIC ACID FRAGMENT - The invention provides a kit for rapidly detecting a target nucleic acid fragment comprising a magnetic bead; an inner primer pair and an outer primer pair suitable for loop-mediated isothermal amplification; and reagents for loop-mediated isothermal amplification. The invention also provides a kit for detecting a pathogen in fish, a method for rapidly detecting a target nucleic acid fragment, and a method for detecting a pathogen in fish. | 06-07-2012 |
Ching-Chun Hsingjen Wang, Tainan TW
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20130244368 | BACKSIDE DEPLETION FOR BACKSIDE ILLUMINATED IMAGE SENSORS - A backside illuminated image sensor is provided which includes a substrate having a front side and a backside, a sensor formed in the substrate at the front side, the sensor including at least a photodiode, and a depletion region formed in the substrate at the backside, a depth of the depletion region is less than 20% of a thickness of the substrate. | 09-19-2013 |
Ching-Hsiang Wang, Tainan TW
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20080316421 | Protective Glasses Assembly - A protective glasses assembly has an integrally formed designed lens, a frame made of a soft material and fitted in with the designed lens and a band. A plurality of spaced apart male portions extend rearward from edges of the designed lens for being inserted into sockets of corresponding covering elements extending forward from edges of the frame, and a number of air-passing grooves are located on upper and lower edges of the frame. The designed lens has engaging blocks respectively formed on left and right sides for engaging with boundary holes of connector members connected with both ends of the band, and through holes for receiving inner inserting sections of the connector members. Thereby the designed lens and the frame can be assembled promptly and kept in a stable position. | 12-25-2008 |
Ching-Yun Wang, Tainan TW
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20090128773 | Eyeglasses with attached second lenses - This invention is to provide a structural combination of eyeglasses with attached second lenses, comprising an eyeglasses frame, a first lenses and a second lenses, where the eyeglasses frame is provided with protruded sockets at the appropriate locations on the left and right of the top rim, and the socket has a trough shaping multiple corners at its internal and having the entry facing ahead, while the second lenses is provided with a pivot rod in the shape of cornered pillar corresponding to each of the trough on the eyeglasses frame, through the cornered-pillar pivot rods are lodged in the cornered-groove troughs of the eyeglasses frame respectively, a firm combination is formed, where the second lenses is then available to be lifted or lowered in front of the first lenses, which achieves to position the clip-on lenses precisely. | 05-21-2009 |
Chun-Chih Wang, Tainan TW
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20110214241 | ROTARY MOP - A rotary mop is provided in which an inner rod body is arranged to be coaxial with an outer rod body. The outer rod body is attached with a transmission stem which is provided with a ratchet block. A drive block inserted with the transmission stem is to engage with the ratchet block. A sleeve is assembled in the inner rod body and helical grooves are provided on the peripheral wall of the sleeve for engaging with guiding posts provided on the drive block. A mop section is mounted on the bottom of the sleeve. In this manner, the transmission stem can move the drive block to rotate the sleeve when the outer rod body is repeatedly pushed and pulled, and the mop section mounted on the bottom of the sleeve can be stably rotated to drain out the water contained in mop strings. | 09-08-2011 |
20110295477 | DEVICE FOR PREVENTING SUDDEN ACCELERATION OF VEHICLE - A device for preventing sudden acceleration of vehicles is revealed. The device includes a vehicle accelerator pedal that is electrically connected with an accelerator pedal sensor (APS), two load feedback signal lines of the APS that are electrically connected with an electronic control unit (ECU) of vehicles and a voltage control unit. The voltage control unit is electrically connected with the APS and is connected with the two load feedback signal lines of the APS in parallel for controlling voltage of the two signal lines. The voltage control unit is electrically connected with a switch unit. Thereby when the two load feedback signal lines operate abnormally and cause unintended acceleration, users turn on the switch unit directly for driving the voltage control unit to reduce the voltage of the two signal lines. Thus the ECU slows engine speed to idle speed so as to prevent the unintended acceleration. | 12-01-2011 |
Chung-Han Wang, Tainan TW
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20100212454 | Bike pedal assembly structure - A bike pedal assembly structure is disclosed, which involves a bracing joint connecting to a crank, and a pivotal shaft of the pedal and a control bar are penetrated into a joining cylinder of the bracing joint for a joining. By depressing the pressing head of the control bar, the pivotal shaft of the pedal and the control bar can be dismounted from the joining cylinder. The pedal can even be mounted to the same structure in a reverse position for the prevention of the possibilities in forgetting to place it somewhere or even in losing it. Since the store of the pedals is located at the space between the cranks of both sides, which means deadly save the space. | 08-26-2010 |
Dean Wang, Tainan TW
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20080286938 | Semiconductor device and fabrication methods thereof - A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings. | 11-20-2008 |
20090321948 | METHOD FOR STACKING DEVICES - A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process. | 12-31-2009 |
20100015792 | Bonding Metallurgy for Three-Dimensional Interconnect - A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate. | 01-21-2010 |
20100047963 | Through Silicon Via Bonding Structure - System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate. | 02-25-2010 |
20110058346 | Bonding Metallurgy for Three-Dimensional Interconnect - A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate. | 03-10-2011 |
20130127049 | Method for Stacking Devices and Structure Thereof - A semiconductor device that has a first device that includes a first through-silicon via (TSV) structure, a first coating material disposed over the first device, the first coating material continuously extending over the first device and covering the first TSV structure, a second device disposed over the first device and within the first coating material, the second device includes a second TSV structure and a plurality of conductive bumps, the plurality of conductive bumps are positioned within the first coating material, a second coating material disposed over the second device, the second coating material continuously extends over the second device and covers the second TSV structure, and a third device disposed over the second coating material, the third device includes a third TSV structure. | 05-23-2013 |
20150137328 | Through Silicon Via Bonding Structure - System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate. | 05-21-2015 |
Dennis Wang, Tainan TW
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20140014974 | LIGHT-EMITTING DEVICE HAVING PATTERNED SUBSTRATE AND METHOD OF MANUFACTURING THEREOF - A light-emitting device disclosed herein comprises a patterned substrate having a plurality of cones, wherein a space is between two adjacent cones. A light-emitting stack formed on the cones. Furthermore, the cones comprise an area ratio of a top area of the cone and a bottom area of the cone which is less than 0.0064. | 01-16-2014 |
Hsinchuan Wang, Tainan TW
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20120240859 | WAFER SUSCEPTOR AND CHEMICAL VAPOR DEPOSITION APPARATUS - A wafer susceptor and a chemical vapor deposition apparatus. In one embodiment, the chemical vapor deposition apparatus includes a chamber, a susceptor, a heater and a gas supply system. The susceptor is disposed within the chamber and is rotatable around a rotation axis, wherein an upper surface of the susceptor is suitable for carrying a plurality of wafers, and a middle region of a lower surface of the susceptor is set with a first cavity. The heater is disposed under the susceptor and is used to heat the wafers on the susceptor. The gas supply system is used to introduce a reactive gas into the chamber. | 09-27-2012 |
Hsin-Hao Wang, Tainan TW
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20140354590 | IN-CELL MULTI-TOUCH PANEL SYSTEM WITH LOW NOISE AND TIME DIVISION MULTIPLEXING AND ITS DRIVING METHOD - An in-cell multi-touch panel system includes: an in-cell touch display panel, a touch display control system. In a first frame time interval, the touch display control system drives the in-cell touch display panel and samples the sensing voltage from the in-cell touch display panel to determine whether there is an approaching external object and noise interference. In a second frame time interval, the touch display control system finds out a frequency with minimum noise for use as a frequency of the touch driving signal when the noise interference exists. In a third frame time interval, the touch display control system is based on the frequency with minimum noise to correspondingly generate the touch driving signal so as to determine whether there is an approaching external object. | 12-04-2014 |
Hung-Sen Wang, Tainan TW
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20100214825 | Programming MRAM Cells Using Probability Write - A method of writing a magneto-resistive random access memory (MRAM) cell includes providing a writing pulse to write a value to the MRAM cell; and verifying a status of the MRAM cell immediately after the step of providing the first writing pulse. In the event of a write failure, the value is rewritten into the MRAM cell. | 08-26-2010 |
20100254181 | Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate - A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector. | 10-07-2010 |
20120127788 | MRAM Cells and Circuit for Programming the Same - A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse. | 05-24-2012 |
20120281464 | Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate - A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector. | 11-08-2012 |
Jen-Pan Wang, Tainan TW
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20130065328 | FOCUS CONTROL METHOD FOR PHOTOLITHOGRAPHY - A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process. | 03-14-2013 |
20130069162 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 03-21-2013 |
20130071957 | System and Methods for Semiconductor Device Performance Prediction During Processing - Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described. | 03-21-2013 |
20130221353 | Methods and Apparatus for Testing Pads on Wafers - Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer. | 08-29-2013 |
20130244139 | Reflective Lithography Masks and Systems and Methods - Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed. | 09-19-2013 |
20130244140 | Non-Planar Lithography Mask and System and Methods - Various non-planar lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a lens-type transparent substrate and a reticle pattern on a surface of the lens-type transparent substrate. The reticle pattern is opaque to optical radiation. Methods for forming similar lithography masks and for using similar lithography masks are disclosed. | 09-19-2013 |
20130285194 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 10-31-2013 |
20140021552 | Strain Adjustment in the Formation of MOS Devices - A method includes forming a gate stack over a semiconductor substrate, and forming a gate spacer on a sidewall of the gate stack. After the step of forming the gate spacer, the gate spacer is etched to reduce a thickness of the gate spacer. A strained layer is then formed. The strained layer includes a portion on an outer sidewall of the gate spacer, and a portion over the gate stack. | 01-23-2014 |
20140117467 | Metal-Oxide-Semiconductor Field-Effect Transistor with Spacer over Gate - A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain. An inner spacer is disposed at least partially over the gate electrode. An outer spacer is disposed adjacent to a sidewall of the gate electrode. | 05-01-2014 |
20140239363 | CAPACITORS COMPRISING SLOT CONTACT PLUGS AND METHODS OF FORMING THE SAME - An integrated circuit includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. An Inter-Layer Dielectric (ILD) is overlying the insulation region. A capacitor includes a first capacitor plate including a first slot contact plug, and a second capacitor plate including a second slot contact plug. The first and the second contact plugs include portions in the ILD. A portion of the ILD between vertical surfaces of the first slot contact plug and the second slot contact plug acts as a capacitor insulator of the capacitor. | 08-28-2014 |
20140252549 | Metal-Insulator-Metal Capacitor - An embodiment metal-insulator-metal (MiM) capacitor includes a gate stack disposed upon an insulation layer, the gate stack including a gate metal, the gate metal serving as a bottom electrode, a dielectric layer disposed upon the gate stack, and a top metal layer disposed upon the dielectric layer, the top metal serving as a top electrode. | 09-11-2014 |
20140264743 | NOVEL STRUCTURE OF METAL GATE MIM - First and second multi-layer structures are formed within respective openings in at least one dielectric layer formed over a semiconductor substrate. The first multi-layer structure comprises a gate electrode, and the second multi-layer structure comprises a resistor and a first electrode of a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure is completed by forming a dielectric film on the at least one dielectric layer and forming a second electrode on the dielectric film. | 09-18-2014 |
20140264750 | Resistor and Metal-Insulator-Metal Capacitor Structure and Method - A passive circuit device incorporating a resistor and a capacitor and a method of forming the circuit device are disclosed. In an exemplary embodiment, the circuit device comprises a substrate and a passive device disposed on the substrate. The passive device includes a bottom plate disposed over the substrate, a top plate disposed over the bottom plate, a spacing dielectric disposed between the bottom plate and the top plate, a first contact and a second contact electrically coupled to the top plate, and a third contact electrically coupled to the bottom plate. The passive device is configured to provide a target capacitance and a first target resistance. The passive device may also include a second top plate disposed over the bottom plate and configured to provide a second target resistance, such that the second target resistance is different from the first target resistance. | 09-18-2014 |
20140293250 | FOCUS CONTROL APPARATUS FOR PHOTOLITHOGRAPHY - A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process. | 10-02-2014 |
20140333914 | Reflective Lithography Masks and Systems and Methods - Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed. | 11-13-2014 |
20150129976 | Semiconductor Device With Silicide Cap - A semiconductor device includes a substrate, an epi-layer, an etch stop layer, an interlayer dielectric (ILD) layer, a silicide layer cap and a contact plug. The substrate has a first portion and a second portion neighboring to the first portion. The etch stop layer is disposed on the second portion. The ILD layer is disposed on the etch stop layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the ILD layer. | 05-14-2015 |
20150243526 | RE-CRYSTALLIZATION FOR BOOSTING STRESS IN MOS DEVICE - A method includes forming a dummy gate stack over a semiconductor substrate, removing the dummy gate stack to form a recess, and implanting a portion of the semiconductor substrate through the recess. During the implantation, an amorphous region is formed from the portion of the semiconductor substrate. The method further includes forming a strained capping layer, wherein the strained capping layer extends into the recess. An annealing is performed on the amorphous region to re-crystallize the amorphous region. The strained capping layer is then removed. | 08-27-2015 |
20150262929 | AIR-GAP SCHEME FOR BEOL PROCESS - The present disclosure relates a method of forming a back-end-of-the-line (BEOL) metallization layer having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a metal interconnect layer within a sacrificial dielectric layer overlying a substrate. The sacrificial dielectric layer is removed to form a recess extending between first and second features of the metal interconnect layer. A protective liner is formed onto the sidewalls and bottom surface of the recess, and then a re-distributed ILD layer is deposited within the recess in a manner that forms an air gap at a position between the first and second features of the metal interconnect layer. The air gap reduces the dielectric constant between the first and second features of the metal interconnect layer. | 09-17-2015 |
20150263092 | SANDWICH EPI CHANNEL FOR DEVICE ENHANCEMENT - The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate. | 09-17-2015 |
20150295060 | Metal Gate Structure and Method - A method comprises forming a gate trench between a plurality of gate spacers over a substrate, forming a resistor trench over the substrate, depositing a first layer on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a second layer over the first layer, depositing a gate electrode layer over the second layer and applying a chemical mechanical polish process to the gate electrode layer until the gate electrode layer is removed from the resistor trench. | 10-15-2015 |
20160086856 | Metal Gate Structure and Method - A method comprises removing a dummy gate electrode layer to form a gate trench in a dielectric layer over a substrate, forming a resistor trench over the substrate, depositing a plurality of films on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a gate electrode layer over the plurality of films and removing an upper portion of the gate electrode layer until the gate electrode layer is removed from the resistor trench. | 03-24-2016 |
Jia-Ching Wang, Tainan TW
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20110122137 | VIDEO SUMMARIZATION METHOD BASED ON MINING STORY STRUCTURE AND SEMANTIC RELATIONS AMONG CONCEPT ENTITIES THEREOF - A video summarized method based on mining the story structure and semantic relations among concept entities has steps of processing a video to generate multiple important shots that are annotated with respective keywords: Performing a concept expansion process by using the keywords to create expansion trees for the annotated shots; rearranging the keywords of the expansion trees and classifying to calculate relations thereof; applying a graph entropy algorithm to determine significant shots and edges interconnected with the shots. Based on the determined result of the graph entropy algorithm, a structured relational graph is built to display the significant shots and edges thereof. Consequently, users can more rapidly browse the content of a video and comprehend if different shots are related. | 05-26-2011 |
Jia-Hui Wang, Tainan TW
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20100079431 | OUTPUT BUFFER AND SOURCE DRIVER USING THE SAME - An output buffer and a source driver for a display panel are provided. The output buffer includes a differential input stage, a bias current source, a feedback module, and an output stage. The differential input stage has a first input terminal and a second input terminal receiving a first input signal and a second input signal respectively, and a first output terminal. The bias module provides a bias current to the differential input stage. The output stage has a second output terminal coupled to the first input terminal for providing an output current to the second output terminal based on a signal of the first output terminal. The feedback module adjusts the bias current and the output current based on the first input signal and the second input signal. The output buffer has ability of switching the output voltage to be low level and high level in high-speed. | 04-01-2010 |
20100103152 | SOURCE DRIVING CIRCUIT WITH OUTPUT BUFFER - A source driving circuit adapted to drive a display panel is provided herein. The source driving circuit includes a first output buffer and a second output buffer responsible for enhancing signals with different polarities respectively. As for the first output buffer, the first output buffer includes a first differential input stage, a first output stage and a second output stage. The first output stage includes a first level adjustment circuit and a first self-bias providing circuit. The first level adjustment circuit provides a first level voltage according to input signals received by the first differential input stage, such that the second output stage thereby provides a first charge current and a second charge current to output a first output signal based on the first level voltage. The first self-bias providing circuit provides a first biased voltage associated with one input signal to control the first level adjustment circuit to operate. | 04-29-2010 |
20100171531 | OUTPUT BUFFER WITH HIGH DRIVING ABILITY - An output buffer including a first differential input stage, a primary output stage, and a secondary output stage is provided herein. The first differential input stage respectively receives a first and a second input signals via a first and a second input terminals. The primary output stage includes a first and a second output stages. The first output stage provides at least one first level voltage according to the first and the second input signals, and the second output stage controlled by the first level voltage drives an output terminal of the output buffer to a target level. The secondary output stage includes a comparator and a third output stage. The comparator compares the induced currents in the first differential input stage, and thereby generates a control voltage. The third output stage controlled by the control voltage drives the output terminal of the output buffer to the target level. | 07-08-2010 |
20110032240 | BUFFERING CIRCUIT WITH REDUCED DYNAMIC POWER CONSUMPTION - A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption. | 02-10-2011 |
20110050665 | SOURCE DRIVER AND COMPENSATION METHOD FOR OFFSET VOLTAGE OF OUTPUT BUFFER THEREOF - A source driver and a compensation method for an offset voltage of an output buffer are provided. The source driver includes a storage element, an output buffer, a sampling unit and a first switch. The output buffer has a first input terminal coupled to the storage element and a second input terminal coupled to an output terminal thereof. The output buffer enhances an input signal of the first input terminal and thereby outputs an output signal via the output terminal. The sampling unit respectively transmits a pixel signal and the output signal to the first input terminal of the output buffer and the storage element during a first sub-period for storing an offset voltage of the output buffer in the storage element. The first switch transmits the pixel signal to the storage during a second sub-period for compensating the pixel signal with the offset voltage stored in the storage element. | 03-03-2011 |
20110050677 | SOURCE DRIVER - A source driver adapted to drive a display panel is provided herein. The source driver includes a first output buffer, a detection module and a conversion module. The first output buffer enhances a first pixel signal and thereby outputs a first enhanced pixel signal. The detection module detects a rise time of the first enhanced pixel signal. The conversion module adjusts a driving capability of the first output buffer in response to the rise time for adjusting a slew rate of the first output buffer. Therefore, the first output buffer in the source driver can dynamically and automatically adjusts the slew rate of the first output buffer through a feedback mechanism composed of the detection module and the conversion module. | 03-03-2011 |
Jia-Shyang Wang, Tainan TW
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20160044256 | METHOD OF ADAPTIVELY REDUCING POWER CONSUMPTION AND AN IMAGE SENSOR THEREOF - A method of adaptively reducing power consumption in an image sensor includes using an electronic rolling shutter to reset pixels of the image sensor row by row. Signal charges are read out from the pixels row by row, followed by obtaining an integration time and a frame height. A power-saving signal is generated when the integration time is substantially greater than the frame height, and at least a circuitry that is not required to operate during an active period of the power-saving signal is turned off. | 02-11-2016 |
20160065872 | IMAGE SENSOR - An image sensor includes readout circuits coupled to read out integrated light signals from pixels via bitlines respectively. Each readout circuit includes a correlated double sampling (CDS) circuit, followed by an analog-to-digital converter (ADC). At least two pixels of a row share a bitline and an associated readout circuit. The ADC operates concurrently with the CDS circuit, such that their operating periods are substantially overlapped with each other. | 03-03-2016 |
Jiu-Yao Wang, Tainan TW
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20110236424 | TREATING ALLERGY WITH DETOXIFIED E. COLI HEAT-LABILE ENTEROTOXIN - A method for treating allergy with a pharmaceutical composition containing a detoxified | 09-29-2011 |
20130302338 | DERMATOPHAGOID PTERONYSSINUS (DER P1) ANTIGEN EPITOPE AND ANTI-DER P1 ANTIBODY - The present invention provides a novel isolated peptide segment which is a | 11-14-2013 |
20160115537 | PROGNOSIS OF CHRONIC OBSTRUCTIVE PULMONARY DISEASE (COPD) AND TREAMENT FOR COPD - The preset invention relates to a method for predicting the disease outcome and/or prognosis of chronic obstructive pulmonary disease (COPD) using a variant of surfactant protein D (SP-D) as a biomarker, which is the G-G-C-C-A haplotype of SP-D. | 04-28-2016 |
Ke-Hsuan Wang, Tainan TW
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20130095551 | METHOD FOR CHANGING CONFORMATION OF GLOBULAR PROTEINS - A method for changing conformation of globular proteins is provided. The method controls the concentration of the globular proteins and the adsorption time of the globular proteins from the aqueous solution to the air/liquid interface, so that the main conformation of the globular proteins in a protein monolayer can be changed into β-sheet or α-helix. Meanwhile, the protein monolayer having the conformation of β-sheet or α-helix can be vertically deposited and transferred onto a substrate for various applications according to needs. The present invention can change three-dimensional structures of biological molecules and remain original functions thereof without additionally using any physical/chemical treatment to change the conformation of the globular proteins. | 04-18-2013 |
Kuan-Hsun Wang, Tainan TW
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20160122355 | CRYSTALLINE FORMS OF PEMETREXED DIACID AND MANUFACTURING PROCESSES THEREFOR - Crystalline forms of pemetrexed diacid are provided (Forms 1 and 2) which are readily produced for either laboratory-scale or industrial scale. Processes for the preparation of Forms 1 and 2 are also provided. | 05-05-2016 |
Liang-Chao Wang, Tainan TW
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20130259956 | Pharmaceutical Kit for Treating Neuronal Damages - A pharmaceutical kit for treating neuronal damages is disclosed. The pharmaceutical composition of the present invention comprises: a first pharmaceutical composition comprising a first effective amount of a Mg | 10-03-2013 |
Liang-Hsiung Wang, Tainan TW
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20120233822 | SAND-REMOVING SEAT BELT BUCKLE - A sand-removing seat belt buckle has a housing and a latching assembly. The housing has a chamber, a first opening and a second opening formed through two ends of the housing, at least one sand cavity formed through a bottom of the housing and being adjacent to the second opening, and at least one support bump formed on an inner bottom of the housing. The latching assembly serves to latch and unlatch an insertion member, and is securely mounted in the housing and on top of the at least one support bump, so that a space is formed between the insertion member and the inner bottom of the housing and communicates with the first opening, the second opening and the sand cavity. Sand, mud and crushed pebbles entering from the first opening can be removed from the sand cavity and the second opening through the space without being deposited inside the seat belt buckle. | 09-20-2012 |
20140289998 | SELF-PROPELLED VACUUM CLEANER - A self-propelled vacuum cleaner has a moving device and a vacuuming device. The moving device has a casing and a control module. The casing has at least one wheel, a vacuuming hole, a clapboard, a mounting chamber, an assembling chamber and a communicating hole. The communicating hole is formed through the clapboard and communicates with the mounting chamber and the assembling chamber. The control module is mounted in the mounting chamber to control the rotation of the at least one wheel. The vacuuming device is detachably connected to the moving device and has a vacuuming module and a filtering module. The vacuuming module is mounted in the assembling chamber and has a front shell, a power supply, a fan and a communicating cover. The filtering module is mounted in the mounting chamber, is connected to the vacuuming module and has a rear shell, a filter holder and a filter. | 10-02-2014 |
Min-Chia Wang, Tainan TW
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20130248089 | METHOD OF MAKING FLEXIBLE IMPLEMENT GRIP WITH SURFACE TEXTURE AND PRINTING - In one version of the method of making a flexible grip, a thin film carrier with negative of desired colored image is laminated to an uncured skin sheet and flat cured in a mold to heat transfer the image to the skin sheet and concurrently form a textured surface. The carrier is peeled away and the skin sheet wrapped and adhesively bonded to a cured underlist. In another version, the thin film carrier with negative of desired image is laminated on an uncured skin sheet which is wrapped on a cured underlist. The wrapped underlist is cured in a textured mold cavity to concurrently, in a single molding operation, heat transfer the image of the skin sheet from a textured surface and cure the skin sheet in place on the underlist. | 09-26-2013 |
20140076487 | METHOD OF MAKING MULTI-COLORED PRINTED SURFACES ON FLEXIBLE IMPLEMENT GRIPS - A method of forming a flexible implement grip utilizing a cured underlist. A sleeve is formed of uncured sheet stock laminated with a carrier having a design thereon of heat transferable colored ink. The laminate is cut to a pattern, wrapped on a core bar and heated in a mold with textured/embossed cavities. The design is heat transferred to the sheet stock in the molding and upon removal from the mold, the carrier and core bar are removed to leave a seamless tubular sleeve with the colored design on the outer surface. The sleeve is then assembled on the underlist and adhesively secured thereon forming a finished grip. | 03-20-2014 |
Ming-Cheng Wang, Tainan TW
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20150035346 | WHEEL COVER FOR TRUCK FRONT WHEELS - A wheel cover for a front wheel of a truck includes a body, a hub cap, at least two washers, multiple bolt caps and an insulation plate. The hub cap is located in the central hole of the body which has multiple recesses evenly defined therein. Each recess has a through hole defined through the inner end thereof. Each recess has a resilient boss and a positioning hole located at the inside thereof. The at least two washers are located in the two of the recesses of the body and each have a notch and an engaging member. The bolt caps are respectively located in the recesses of the body and each bolt cap has multiple ridges extending from the inside of the space of each bolt cap. The insulation plate is located at the inside of the body. | 02-05-2015 |
20150035348 | WHEEL COVER FOR TRUCK REAR WHEELS - A wheel cover for a rear wheel of a truck includes a body, a hub cap and multiple bolt caps. The body has multiple recesses defined therein and each recess has a through hole defined through the inner end thereof Each recess has a resilient protrusion on the inside thereof The hub cap is mounted to the passage of the body. The bolt caps are respectively located in the recesses of the body and each bolt cap has multiple engaging recesses defined in outside thereof The resilient protrusions of the body are engaged with the engaging recesses to fix the bolt caps in the recesses of the body. | 02-05-2015 |
20150173953 | PROTECTION MASK - A protection mask includes a frame having two slits in two ends thereof and a tongue is located in each slit. Two temples extend backward from the two ends of the frame. A connection rod is located at the middle portion of the frame. A connector is connected to the connection rod and has a C-clip which has a notch. A protrusion extends from the connector and has a groove defined in the outside thereof. A nose pad is connected to the connection rod and has a snapping portion which is engaged with the notch of the connector. The snapping portion has a snapping slot. A protection member has an insertion slot with which the protrusion of the connector is engaged. Two connection slots are respectively defined in two ends of the protection member. The two tongues are engaged with the two connection slots. | 06-25-2015 |
Ming-Jiun Wang, Tainan TW
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20100220893 | Method and System of Mono-View Depth Estimation - A method and system of mono-view depth estimation are disclosed. A two-dimensional (2D) image is first segmented into a number of objects. A depth diffusion region (DDR), such as the ground or a floor, is then detected among the objects. The DDR generally includes a horizontal plane. The DDR is assigned the depth, and each object connected to the DDR is assigned depth according to the depth of the DDR at the connected site. | 09-02-2010 |
20100220924 | Method and System of Extracting A Perceptual Feature Set - A method and system of extracting a perceptual feature set for image/video segmentation are disclosed. An input image is converted to obtain a hue component and a saturation component, where the hue component is quantized into a number of quantum values. After weighting the quantized hue component with the saturation component, the weighted quantized hue component and the saturation component are subjected to a statistical operation in order to extract feature vectors. Accordingly, the method and system provide overall segmentation results that are very close to human interpretation. | 09-02-2010 |
Ming-Shan Wang, Tainan TW
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20140328872 | Formula of Suppressing Viability of Tumor Cells and a Medication Thereof - A formula of suppressing viability of tumor cells is disclosed. The formula comprises 27.3-50.0 wt % of | 11-06-2014 |
Min-Hsieng Wang, Tainan TW
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20150158257 | ADAPTER FOR SWITCHING LIQUID PATCH DEVICE AND AIR PUMP - An adapter for switching liquid patch device and air pump includes a body which has an air intake path, an air outgoing path, a liquid outgoing path and a tire connection path. The air outgoing path and the liquid outgoing path are connected to the liquid bottle. The air intake path and the tire connection path are respectively connected with the pump connector and the tire connector. The body has an air inlet, an air outlet, a liquid outlet and a tire connection hole. The air inlet, the air outlet, the liquid outlet and the tire connection hole are respectively connected with the air intake path, the air outgoing path, the liquid outgoing path and the tire connection path. A stationary ceramic disk, a movable ceramic disk, and a knob are respectively installed to the installation face of the body. The knob is rotated to operate the air-pumping position and liquid-introducing position. | 06-11-2015 |
Min-Lang Wang, Tainan TW
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20160043686 | WATERTIGHT ROOF ASSEMBLY INTEGRATED WITH SOLAR PANELS - A watertight roof assembly integrated with solar panels to construct a roof of a building includes a plurality of support units spaced from each other, a plurality of solar modules straddled two neighboring support units, a plurality of fixture units and a plurality of waterproof units corresponding respectively to one solar module. Each support unit includes two bearing planes and a plurality of holding racks located between the two bearing planes. Each solar module has two sides leaned respectively on one of the abutting bearing planes of the two support units. Each fixture unit has a connecting portion, an extension and a press portion. Each waterproof unit has a first press strip and a second press strip. | 02-11-2016 |
Peter Wang, Tainan TW
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20080314949 | Bit-Carrying Device - A bit-carrying device includes an axle and a plurality of sleeves each including a longitudinal through-hole mounted around an outer periphery of the axle. Each sleeve includes at least one coupling portion on an outer circumference thereof for coupling with a bit. A handle is mounted to an upper end of the axle for easy carriage. The longitudinal through-hole of each sleeve includes an inner periphery in frictional contact with the outer periphery of the axle to prevent relative rotation therebetween. Each sleeve can be forcibly turned relative to the axle to a desired position. | 12-25-2008 |
Ping-Tien Wang, Tainan TW
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20090317178 | Tube folder - A tube folder includes a top shell, a bottom shell and an instant clasp set; wherein the top shell is provided with two sets of lug holes; the bottom shell is provided with two plug tubes; the instant clasp set covers a dismount handle which has a set of joined segments at its terminal, and an empty space formed in between the two joined segments; and a shaft, fitted in the empty space of the joined segments; each set of the lug holes and corresponding plug tube has been bound by a hinge, so does the joined segments of the dismount handle and the shaft; the surfaces of the top and the bottom shells are shaped into reinforcing ribs, providing handy fitting and enhanced joint when connecting to the tubes. | 12-24-2009 |
Ru-Wen Wang, Tainan TW
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20140299044 | Pressure gauge - A pressure gauge includes a base including an annular flange and a pipe for gas flow; a ring on the flange; an uneven pressure measuring member on the ring; a moveable assembly including a seat, a hollow insert, and a shaft wherein the seat is secured to the pressure measuring member, the insert includes two opposite, internal, upper projections, the insert is fastened in the seat, the shaft includes external threads secured to the projections, an upper annular groove, a top protrusion, and an axis projects upward from the protrusion; a pointer secured to the axis; a covering member includes a ring member on the pressure measuring member, and a bridge crossing the ring member and allowing the axis to pass through, and a bent member; a balance spring in the groove and fastened in the bent member; a scale on the bridge; a housing; and a transparent cover. | 10-09-2014 |
20160123825 | Structure of pressure gauge - An improved structure of pressure gauge includes a bottom case, a pressure measurement assembly, a rotating assembly, a fulcrum piece, a coil spring, a scale meter, and an outer case. The pressure measurement assembly is installed above the bottom case and the surface thereof is shaped with concentric circular waves. The rotating assembly includes a sleeve body and a central rod. A fulcrum piece is installed across between the sleeve body and the central rod. A plurality of through holes and a coil retaining base are provided on the fulcrum piece. One end of the coil spring is screwed onto the coil slot and the other end thereof is installed on the coil retaining base. The outer case is located in the outer area of the bottom case and the fulcrum piece. A transparent cover body is installed on top of the outer case. | 05-05-2016 |
Sheng-Yi Wang, Tainan TW
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20080231586 | DRIVING METHOD OR APPARATUS FOR FLAT PANEL DISPLAY DEVICE - A driving circuit board for a flat panel display device includes a substrate having a first surface and a second, opposite surface. A first timing controller is disposed on the first surface, and a second timing controller is disposed on the second surface of the substrate. At least one electrically conductive line electrically connects input terminals of the first and second timing controllers through the substrate. | 09-25-2008 |
Shih-Hsien Wang, Tainan TW
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20140143411 | NETWORK DEVICE AND METHOD OF PROCESSING DYING GASP - A network device is provided, which is connected to a receiver. The network device includes a signal processing unit and a transceiver unit. Prior to occurrence of a hardware interrupt event, the signal processing unit detects the connection configuration between the network device and the receiver and outputs a temporary signal corresponding to the configuration of connection. The transceiver unit, which is connected to the signal processing unit and the receiver, receives and stores the temporary signal so that, when a hardware interrupt event occurs, the transceiver unit generates a dying gasp corresponding to the temporary signal and transmits the dying gasp to the receiver. | 05-22-2014 |
Shu-Chen Wang, Tainan TW
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20130052171 | IMMUNOMODULATORY ISOLATED LACTOBACILLUS STRAINAND APPLICATION THEREOF - An immunomodulatory isolated | 02-28-2013 |
Shyh-Shyan Wang, Tainan TW
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20110302838 | Method And Apparatus For Nurturing Phalaenopsis Orchid Seedlings With Stalk With High Performance of Land Use - The present invention provides a method and an apparatus for nurturing phalaenopsis orchid seedlings with stalk with a high performance of land use, and comprises a nurture room having an air conditioning equipment for a temperature control; a multi-layer planting bed rack installed in the nurture room for placing the phalaenopsis orchid seedlings; and an illumination rack fixed above each planting bed, and having an artificial light source installed thereon for illuminating the phalaenopsis orchid seedlings in the planting beds. With the aforementioned arrangement, the large quantity of phalaenopsis orchid seedlings placed on each planting bed are grown under the conditions controlled at a temperature at 17° C. ˜25° C. and a light intensity of 100˜11000 Lux, so as to achieve the effects of improving the production efficiency, lowering the cost and providing a stable shipping time. | 12-15-2011 |
Sih-Kai Wang, Tainan TW
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20090122678 | DEVICE AND METHOD FOR GENERATING TRACK-CROSSING SIGNAL IN OPTICAL DISC DRIVE - A track-crossing signal generator includes a bottom envelope detecting unit, a defect detector, an auto gain control unit, and an amplifier. The bottom envelope detecting unit receives a radio frequency signal, and outputs a bottom envelope signal. The defect detector is electrically connected to the bottom envelope detecting unit for receiving the bottom envelope signal and generating a defect signal when a defect area is formed on a disc track. The auto gain control unit is electrically connected to the bottom envelope detecting unit for receiving the bottom envelope signal and dynamically adjusting a gain value according to the amplitude of the bottom envelope signal. The amplifier is electrically connected to the bottom envelope detecting unit and the auto gain control unit for receiving the bottom envelope signal and dynamically adjusting the bottom envelope signal according to the gain value, thereby amplifying the bottom envelope signal as a track-crossing signal. | 05-14-2009 |
20090135694 | DEVICE AND METHOD FOR DETECTING DISC DEFECT - A method for detecting a typical defect area on a disc track includes the following steps. Firstly, a source signal is provided. Then, first and second signals are generated according to the source signal. The first and second signals are held at the peak level of the source signal and respectively decreased at first and second drop rates. Then, first and second threshold values are subtracted from the first and second signals to generate first and second slice signals, respectively. Afterwards, the source signal is compared with either the first slice signal or the second slice signal. When the first slice signal is larger than the source signal, a typical defect signal is changed from a first level to a second level. Whereas, the typical defect signal is changed from the second level to the first level when the second slice signal is smaller than the source signal. | 05-28-2009 |
Simon Wang, Tainan TW
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20080304944 | Preventing Contamination in Integrated Circuit Manufacturing Lines - A semiconductor manufacturing line includes an inert environment selected from the group consisting essentially of an inert airtight wafer holder, an inert wafer transport channel, an inert production tool, an inert clean room, and combinations thereof. | 12-11-2008 |
Ting-Yu Wang, Tainan TW
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20120141989 | KIT AND METHOD FOR RAPIDLY DETECTING A TARGET NUCLEIC ACID FRAGMENT - The invention provides a kit for rapidly detecting a target nucleic acid fragment comprising a magnetic bead; an inner primer pair and an outer primer pair suitable for loop-mediated isothermal amplification; and reagents for loop-mediated isothermal amplification. The invention also provides a kit for detecting a pathogen in fish, a method for rapidly detecting a target nucleic acid fragment, and a method for detecting a pathogen in fish. | 06-07-2012 |
Tongjung Wang, Tainan TW
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20090167660 | LIQUID CRYSTAL DISPLAY AND CONTROL METHOD THEREOF - A liquid crystal display and a control method thereof are disclosed. The pixel of the liquid crystal display comprises: a first switch element, a second switch element, a first storage capacitor, a second storage capacitor, a first liquid crystal capacitor, and a second liquid crystal capacitor. The control method comprises: providing a first sub-pixel charge stage, a second sub-pixel charge stage, and a normal display stage. The first sub-pixel charge stage comprises: turning on the first switch element and the second switch to input a first gray level signal to the first storage capacitor, the second storage capacitor, the first liquid crystal capacitor, and the second liquid crystal capacitor. The second sub-pixel charge stage comprises: turning off the second switch element and inputting a second gray level signal to the first storage capacitor and the first liquid crystal capacitor. The normal display stage comprises: turning off the first switch element. | 07-02-2009 |
Tsung-Ding Wang, Tainan TW
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20100102453 | Three-Dimensional Integrated Circuit Stacking-Joint Interface Structure - A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV. | 04-29-2010 |
20100117201 | Cooling Channels in 3DIC Stacks - An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through. | 05-13-2010 |
20100225011 | System and Method for Integrated Circuit Fabrication - A system and method for integrated circuit fabrication is provided. A wafer holding system includes a wafer carrier that holds the wafer at a specified alignment, and a top ring disposed on a top surface of the wafer and of the wafer carrier. The top ring holds the wafer and the wafer carrier together as a single unit. The wafer carrier includes an alignment mechanism to hold the wafer in the specified alignment. | 09-09-2010 |
20100244284 | METHOD FOR ULTRA THIN WAFER HANDLING AND PROCESSING - A method for thin wafer handling and processing is provided. In one embodiment, the method comprises providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side. A plurality of dies are attached to the first side of the wafer, at least one of the dies are bonded to at least one of the plurality of semiconductor chips. A wafer carrier is provided, wherein the wafer carrier is attached to the second side of the wafer. The first side of the wafer and the plurality of dies are encapsulated with a planar support layer. A first adhesion tape is attached to the planar support layer. The wafer carrier is then removed from the wafer and the wafer is diced into individual semiconductor packages. | 09-30-2010 |
20100279463 | METHOD OF FORMING STACKED-DIE PACKAGES - A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer. | 11-04-2010 |
20110051378 | Wafer-Level Molded Structure for Package Assembly - An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound. | 03-03-2011 |
20110062592 | Delamination Resistance of Stacked Dies in Die Saw - An integrated circuit structure includes a first die including TSVs; a second die over and bonded to the first die, with the first die having a surface facing the second die; and a molding compound including a portion over the first die and the second die. The molding compound contacts the surface of the second die. Further, the molding compound includes a portion extending below the surface of the second die. | 03-17-2011 |
20120168962 | THIN WAFER PROTECTION DEVICE - A thin wafer protection device includes a wafer having a plurality of semiconductor chips. The wafer has a first side and an opposite second side. A plurality of dies is over the first side of the wafer, and at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips. A wafer carrier is over the second side of the wafer. An encapsulating layer is over the first side of the wafer and the plurality of dies, and the encapsulating layer has a planar top surface. An adhesive tape is over the planar top surface of the encapsulating layer. | 07-05-2012 |
20120302008 | Packaging Jig and Process for Semiconductor Packaging - An embodiment is a method for semiconductor packaging. The method comprises attaching a chip to a carrier substrate through a first side of a jig, the chip being attached by bumps; applying balls to bond pads on the carrier substrate through a second side of the jig; and simultaneously reflowing the bumps and the balls. According to a further embodiment, a packaging jig comprises a cover, a base, and a connector. The cover has a first window through the cover. The base has a second window through the base. The first window exposes a first surface of a volume intermediate the cover and the base, and the second window exposes a second surface of the volume. The first surface is opposite the volume from the second surface. The connector aligns and couples the cover to the base. | 11-29-2012 |
20130032923 | Integrated Inductor - A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization. | 02-07-2013 |
20130056880 | SYSTEM IN PACKAGE AND METHOD OF FABRICATING SAME - An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die. | 03-07-2013 |
20130075139 | Formation of Connectors without UBM - A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer. | 03-28-2013 |
20130093084 | Wafer-Level Chip Scale Package with Re-Workable Underfill - A package includes a printed circuit board (PCB), and a die bonded to the PCB through solder balls. A re-workable underfill is dispensed in a region between the PCB and the die. | 04-18-2013 |
20130113108 | SYSTEM IN PACKAGE PROCESS FLOW - A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate. | 05-09-2013 |
20130113115 | SYSTEM IN PACKAGE PROCESS FLOW - A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate. | 05-09-2013 |
20130119549 | Mold Chase Design for Package-on-Package Applications - A method includes placing a mold chase over a bottom package, wherein the bottom package has a connector at a top surface of the bottom package. The mold chase includes a cover, and a pin under and connected to the cover. The pin occupies a space extending from a top surface of the connector to the cover. A polymer is filled into a space between the cover of the mold chase and the bottom package. The polymer is then cured. After the step of curing the polymer, the mold chase is removed, and the connector is exposed through an opening in the polymer, wherein the opening is left by the pin of the mold chase. | 05-16-2013 |
20130168856 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die. | 07-04-2013 |
20130187269 | PACKAGE ASSEMBLY AND METHOD OF FORMING THE SAME - A package assembly including a semiconductor die electrically coupled to a substrate by an interconnected joint structure. The semiconductor die includes a bump overlying a semiconductor substrate, and a molding compound layer overlying the semiconductor substrate and being in physical contact with a first portion of the bump. The substrate includes a no-flow underfill layer on a conductive region. A second portion of the bump is in physical contact with the no-flow underfill layer to form the interconnected joint structure. | 07-25-2013 |
20130256914 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - The described embodiments of forming bonding structures for package on package involves removing a portion of connectors and molding compound of the lower package. The described bonding mechanisms enable easier placement and alignment of connectors of an upper package to with connector of a lower package. As a result, the process window of the bonding process is wider. In addition, the bonding structures have smoother join profile and planar joint plane. As a result, the bonding structures are less likely to crack and also are less likely to crack. Both the yield and the form factor of the package on package structure are improved. | 10-03-2013 |
20130270698 | STRAIN REDUCED STRUCTURE FOR IC PACKAGING - A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio of the first conductive pad over the third bonding pad at an inner region is different from a width ratio of the second conductive pad over the fourth bonding pad at an outer region. | 10-17-2013 |
20130270705 | Semiconductor Device Packages and Methods - Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate. | 10-17-2013 |
20140001644 | Package Structures and Methods for Forming the Same | 01-02-2014 |
20140042623 | SYSTEM IN PACKAGE AND METHOD OF FABRICATING SAME - An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die. | 02-13-2014 |
20140048926 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer. | 02-20-2014 |
20140103540 | Cooling Channels in 3DIC Stacks - An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through. | 04-17-2014 |
20140124916 | Molded Underfilling for Package on Package Devices - Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall. | 05-08-2014 |
20140131894 | POP Structures with Air Gaps and Methods for Forming the Same - A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die. | 05-15-2014 |
20140183725 | POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump. | 07-03-2014 |
20140197547 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector. | 07-17-2014 |
20140206140 | Method of Forming Wafer-Level Molded Structure for Package Assembly - A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units. | 07-24-2014 |
20140252609 | Package-on-Package Structure and Methods for Forming the Same - A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material. | 09-11-2014 |
20140346669 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a passivation layer overlying a semiconductor substrate, a pillar bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer. | 11-27-2014 |
20150187734 | Packages with Die Stack Including Exposed Molding Underfill - A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die. | 07-02-2015 |
20150214181 | METHODS FOR FORMING A SEMICONDUCTOR DEVICE PACKAGE - A method of forming a semiconductor device package includes bonding a first connector to a first conductive structure on a first package. The method includes bonding a die to a surface of the first package, wherein a top surface of the first connector extends above a top surface of the die. The method includes surrounding the first connector with a molding compound. The method includes removing a portion of the first connector and a portion of the molding compound. The top surface of the remaining first conductor is below the top surface of the die. A first top surface of the remaining molding compound is below the top surface of the die. A second top surface of the remaining molding compound is level with the top surface of the die. The method includes bonding a second connector to the remaining portion of the first connector. | 07-30-2015 |
20150214191 | Packages with Stacked Dies and Methods of Forming the Same - A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate. | 07-30-2015 |
20150228587 | Concentric Bump Design for the Alignment in Die Stacking - An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other. | 08-13-2015 |
20150235936 | SUBSTRATE DESIGN FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME - An embodiment device includes a first die, a first molding compound extending along sidewalls of the first die, and one or more first redistribution layers (RDLs) on the first die and the first molding compound. The device further includes a device package comprising a plurality of second dies, wherein the device package is bonded to an opposing surface of the one or more first RDLs as the first die and the first molding compound. A package substrate is bonded to the opposing surface of the one or more first RDLs. The package substrate is electrically connected to the first die and the plurality of second dies. | 08-20-2015 |
20150235989 | SUBSTRATE DESIGN FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME - An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edges of the first die. The device package further includes one or more second dies bonded to a first surface of the one or more RDLs and a connector element on the first surface of the one or more RDLs. The connector element has a vertical dimension greater than the one or more second dies. A package substrate is bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate. | 08-20-2015 |
20150235990 | SUBSTRATE DESIGN FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME - An embodiment device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity. | 08-20-2015 |
20150235993 | Thermal Performance Structure for Semiconductor Packages and Method of Forming Same - An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole. | 08-20-2015 |
20150249066 | METHOD OF FORMING PACKAGE ASSEMBLY - A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer. | 09-03-2015 |
20150262900 | Dam for Three-Dimensional Integrated Circuit - An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure. | 09-17-2015 |
20150262956 | Package Substrates, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices - In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer. | 09-17-2015 |
20150262973 | 3D INTEGRATED CIRCUIT PACKAGE PROCESSING WITH PANEL TYPE LID - Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess. | 09-17-2015 |
20150303163 | UNDERFILL DISPENSING WITH CONTROLLED FILLET PROFILE - A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package. | 10-22-2015 |
20150318271 | Method of Forming Wafer-Level Molded Structure for Package Assembly - A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units. | 11-05-2015 |
20150364386 | Stacked Semiconductor Devices and Methods of Forming Same - Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to form first tier stacks, the semiconductor device comprising one or more integrated circuit dies, the semiconductor device having one or more test pads per integrated circuit die on the top surface of the semiconductor device. Each of the first tier stacks is electrically tested to identify first known good stacks and first known bad stacks. Second tier workpieces are mounted atop the first known good stacks, thereby forming second tier stacks. Each of the second tier stacks is electrically tested to identify second known good stacks and second known bad stacks. Stacking process further comprises one or more workpiece mounting/testing cycles. The stacking process continues until the stacked semiconductor devices comprise desired number of workpieces. | 12-17-2015 |
20150364436 | Integrated Circuit Packages and Methods of Forming Same - Integrated circuit (IC) packages and methods of forming the IC packages are provided. In an embodiment, IC dies are formed and are placed on a carrier to form a packaged semiconductor device. An encapsulant is formed over the IC dies and between the neighboring IC dies. The encapsulant and the IC dies are planarized to expose contacts on top surfaces of the IC dies, and redistribution layers (RDLs) are formed over the planarized encapsulant and the planarized IC dies. Openings are formed in a topmost dielectric layer of the RDLs to expose interconnects in the RDL, and a conductive seed layer is formed over the RDL and in the openings. Connectors of a first type and connectors of a second type are formed over the seed layer in the openings. The packaged semiconductor device is diced into individual IC packages. | 12-17-2015 |
20150380275 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region. | 12-31-2015 |
20160056087 | PACKAGE-ON-PACKAGE STRUCTURE WITH ORGANIC INTERPOSER - A device comprises a substrate having a die mounted on the first side of the substrate and a moldable underfill (MUF) disposed on the first side of the substrate and around the die. An interposer is mounted on the first side of the substrate, with the interposer having lands disposed on a first side of the interposer. The interposer mounted to the substrate by connectors bonded to a second side of the interposer, the connectors providing electrical connectivity between the interposer and the substrate. A package is mounted on the first side of the interposer and is electrically connected to the lands. At least one of the lands is aligned directly over the die and wherein a pitch of the connectors is different than a pitch of the lands. | 02-25-2016 |
Tzu-Chien Wang, Tainan TW
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20100054854 | Quick-Release Coupler - A quick-release coupler includes a rod having first and second sections. The first section includes an end for coupling with a pneumatic tool. The second section extends from the other end of the first section. A sleeve is slideably mounted around the rod and includes an end for releasably coupling a bit. The sleeve includes an axial bore having larger and smaller sections. The larger section has polygonal cross sections corresponding to polygonal cross sections of the first section. A radial bore is formed in the sleeve and in communication with the smaller section. A ball is moveably received in the radial bore and moveably received in a recess of the second section of the rod to releasably engage the sleeve with the bit. A spring is mounted in the larger section of the sleeve for biasing the sleeve towards the other end of the rod. | 03-04-2010 |
Tzung-Ren Wang, Tainan TW
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20100289953 | SYSTEM AND METHOD FOR PROCESSING MULTIMEDIA DATA USING AN AUDIO-VIDEO LINK - A multimedia processor includes an audio processor configured to process an audio input signal to generate an audio output signal and an assistant signal, and a video processor coupled with the audio processor and configured to process video input signal and the assistant signal to generate a video output signal simultaneously according to the video input signal and the assistant signal. Provided with the assistant signal, the video processor acquires more video processing-related information for rendering video content in a more realistic manner. Mal-motion detection can thus be prevented, and video quality can be improved. | 11-18-2010 |
20110113172 | UTILIZATION-ENHANCED SHARED BUS SYSTEM AND BUS ARBITRATION METHOD - A utilization-enhanced shared bus system and bus arbitration method are disclosed. An arbiter arbitrates among multiple masters according to active requests sent from the masters. The arbiter sends a passive request to one of the masters in an idle period of the shared bus according to respective status of the masters. Accordingly, the master that receives the passive request may access a shared resource in the idle period. | 05-12-2011 |
20120044241 | THREE-DIMENSIONAL ON-SCREEN DISPLAY IMAGING SYSTEM AND METHOD - The present invention is directed to a 3D OSD imaging system and method. A depth generator generates at least one image depth map according to a 2D image, and an image mixer superimposes an OSD image on the 2D image, thereby resulting in a 2D image with OSD. An OSD unit provides an OSD depth map and the OSD image, and a depth mixer superimposes the OSD depth map on the image depth map, thereby resulting in a composite depth map. A depth-image-based rendering (DIBR) unit generates a left image and a right image according to the 2D image with OSD and the composite depth map. | 02-23-2012 |
Tzu-Wen Wang, Tainan TW
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20100170786 | REFURBISHED SPUTTERING TARGET AND METHOD FOR MAKING THE SAME - A method for making a refurbished sputtering target has steps of providing a spent target with a backside, an eroded side and a rim; mechanically pre-treating the backside of the spent target; applying powder material that has the same composition as the spent target to form a powder-filled layer; and sequentially pre-pressing and sintering the spent target with the powder-filled layer to obtain the refurbished sputtering target. Therefore, a percentage of the spent target is reduced by mechanically treating the backside of the spent target, so the refurbished sputtering target has a consistent quality. | 07-08-2010 |
20120037500 | HOLLOW TARGET ASSEMBLY - A hollow target assembly has a support tube, a target body and a plurality of elastic elements. The target body includes a plurality of hollow target materials and they pass through the support tube sequentially and locate at the outer surface of the support tube. By the grooves formed and extended from an end of the inside wall of the hollow target material and the corresponding concaves formed at the outside wall of the support tube, the elastic elements can lean and be positioned in the space generated by the grooves and corresponding concaves. Therefore, the target body and the support tube are brought together closely by these elastic elements in a simple and a low-cost way. | 02-16-2012 |
Wei-Chi Wang, Tainan TW
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20100116353 | INFLATING NOZZLE ASSEMBLY - An inflating nozzle assembly has a housing, two nozzles and a pushing device. The housing has two nozzle chambers and two outlets. The nozzles are mounted respectively in the first nozzle chamber, and one of the nozzles has a nozzle body, a nozzle rod and a spring. The nozzle body has at least one inlet. The nozzle rod is movably mounted in the nozzle body and has a sealing protrusion to divide two communication segments in the nozzle body. The spring is connected to the nozzle rod to keep one of the communication segments of the axial hole from communicating with the at least one inlet in the first nozzle body. Accordingly, an airflow led through the outlets of the housing can be automatically switched by inserting different types of air valves into the corresponding outlets. | 05-13-2010 |
20100300350 | Pressure gauge - A pressure gauge has a base, a measuring assembly, a dial and a fastener. The base has a chamber and a side opening communicating with the chamber. The measuring assembly is mounted in the chamber and has a tab mount passing through the side opening. The tab mount has a fixing hole. The dial is disposed on the base, covers the measuring assembly and has a tab and a fastening hole. The tab extends through the side opening of the base. The fastening hole is formed through the tab and aligns with the fixing hole of the tab mount. The fastener is mounted through the fixing hole and the fastening hole and thus fixes the dial without being revealed. Therefore aesthetic appearance of the pressure gauge is improved. | 12-02-2010 |
20150322935 | ELECTRICAL INFLATOR - An electrical inflator has a cylindrical shell, an electrical aeration pump, an illumination assembly, a cell base and a switch assembly. The cylindrical shell has a tube, a front cover and a rear cover. The electrical aeration pump is mounted in the tube near the front cover and has a gas outlet located in the tube. The illumination assembly is mounted in the tube towards the front cover. The cell base is mounted in the tube behind the electrical aeration pump. The cell base has at least one cell. The switch assembly is mounted in the tube and electrically connects to the cell base, the electrical aeration pump and the illumination assembly. | 11-12-2015 |
Wen-Ting Wang, Tainan TW
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20150064475 | SAFETY AGGLUTINATION GLASS STRUCTURE - The invention relates to a safety agglutination glass structure, comprising two glass substrates and a heat insulating adhesive membrane. The heat insulating adhesive membrane constituted of heat insulating particles and a colloid material is disposed between the two glass substrates. Therefore, the two glass substrates can combine together by heating and pressurizing for the purpose of simplifying processing procedures, reducing the costs and preventing distortion. | 03-05-2015 |
Wu-Li Wang, Tainan TW
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20130250404 | OPTICAL LENS AND METHOD OF MAKING THE SAME - An optical lens includes a lens member and two shade layers on opposite sides of the lens member. The lens member respectively has a lens portion on each side thereof. Each shade layer has an aperture above the corresponding lens portion of the lens member to serve the function of aperture. A method uses optical lithography technique to make such optical lens in a fast way, and the shade layers will have a strong bonding strength with the lens member. | 09-26-2013 |
20130270426 | LENS MODULE - A lens module for transforming optical signals into electrical signals includes an image sensor provided at a tail of an optical axis to transform optical signals into electrical signals; a first lens provided on the image sensor, wherein the first lens has at least a non-flat lens portion; and a second lens provided on the first lens, wherein the second lens has at least a non-flat lens portion. | 10-17-2013 |
20130270725 | METHOD OF MAKING LENS - A method of making lenses includes the following steps: A. Provide a photo-curing material into a cavity between a first die and a second die. B. Expose the photo-curing material under predetermined light, whereby the photo-curing material is solidified, and a transmittance of the solidified photo-curing material is greater than 75%. C. Remove the first die and the second die to obtain a lens material; and D. Cut the lens material to obtain a plurality of lenses. | 10-17-2013 |
20130271853 | OPTICAL LENS ASSEMBLY - An optical lens assembly includes a first lens, an adhesive layer, and a second lens in sequence. The adhesive layer is made of adhesive macromolecular compounds to adhere both sides thereof to interior sides of the first lens and the second lens, and the adhesive layer has following conditions: a transmittance greater than 70%; |n3−n1|<0.5; and |n3−n2|<0.5; where n1 is a refractive index of the first lens; n2 is a refractive index of the second lens; and n3 is a refractive index of the adhesive layer. | 10-17-2013 |
20130271854 | COMBINATION LENS - A combination lens includes a first lens having a first lens portion on a side thereof and at least a protrusion around the first lens portion, and a second lens having a second lens portion on a side thereof and at least a recess around the second lens portion. The first lens is bonded to the second lens by engaging the protrusion with the recess. Therefore, the engagement of the protrusion and the recess may fix the first and the second lenses in a right position before the glue solidified. | 10-17-2013 |
20130273241 | METHOD OF MAKING LENS - A method of making lenses includes the following steps: A. Provide a photo-curing material into a cavity between a first die and a second die. B. Expose the photo-curing material under predetermined light, whereby the photo-curing material is solidified, and a transmittance of the solidified photo-curing material is greater than 75%. C. Remove the first die and the second die to obtain a lens material; and D. Cut the lens material to obtain a plurality of lenses. | 10-17-2013 |
20130334400 | METHOD OF MAKING LENS MODULES AND THE LENS MODULE - A method of making lens modules includes the following steps: Put a plurality of lens members between a first die and a second die, wherein the first die touches the substrate of each lens module, and the second die touches the lens of each lens module. Provide a housing material between the first die and the second die, and then solidify the housing material. Remove the first die and the second die to obtain a block; and Cut the block to obtain a plurality of lens modules. | 12-19-2013 |
20140376116 | OPTICAL LENS ASSEMBLY - An optical lens assembly includes a first lens, an adhesive layer, and a second lens in sequence, wherein the first and the second lenses are rectangular in shape. The adhesive layer is made of an adhesive acrylic composition. to adhere both sides thereof to interior sides of the first lens and the second lens, and the adhesive layer has following conditions: a transmittance greater than 70%; |n3−n1 |<0.5; and |n3−n2 |<0.5; where n1 is a refractive index of the first lens; n2 is a refractive index of the second lens; and n3 is a refractive index of the adhesive layer. | 12-25-2014 |
Yao-Chang Wang, Tainan TW
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20110049722 | Semiconductor Circuit Structure and Layout Method thereof - A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure. | 03-03-2011 |
Yeongfeng Wang, Tainan TW
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20090167660 | LIQUID CRYSTAL DISPLAY AND CONTROL METHOD THEREOF - A liquid crystal display and a control method thereof are disclosed. The pixel of the liquid crystal display comprises: a first switch element, a second switch element, a first storage capacitor, a second storage capacitor, a first liquid crystal capacitor, and a second liquid crystal capacitor. The control method comprises: providing a first sub-pixel charge stage, a second sub-pixel charge stage, and a normal display stage. The first sub-pixel charge stage comprises: turning on the first switch element and the second switch to input a first gray level signal to the first storage capacitor, the second storage capacitor, the first liquid crystal capacitor, and the second liquid crystal capacitor. The second sub-pixel charge stage comprises: turning off the second switch element and inputting a second gray level signal to the first storage capacitor and the first liquid crystal capacitor. The normal display stage comprises: turning off the first switch element. | 07-02-2009 |
Yi-Chang Wang, Tainan TW
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20150161783 | TRACKING EYE RECOVERY - A method and system for tracking eye recovery. The method includes: receiving eye data from an eyewear, wherein the eye data includes images acquired by an image capturing device in the eyewear; analyzing the eye data to determine an eye recovery status, wherein the analyzing is carried out by comparing the eye data to an initial set of eye conditions; and providing a notification of the eye recovery status. | 06-11-2015 |
Yu-Cheng Wang, Tainan TW
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20110189859 | Method of Etching Oxide Layer and Nitride Layer - An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching. | 08-04-2011 |
Yu-Ching Wang, Tainan TW
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20080232966 | Detachable blade assembly for horizontal-axis wind turbine - A blade assembly for a horizontal-axis wind turbine includes a hub, and a plurality of detachable blade units each mounted on a periphery of the hub and each including a plurality of blades detachably connected with each other by a plurality of connecting devices. Thus, the blade assembly comprises a hub and a plurality of detachable blade units so that all parts of the blade assembly are detachable to reduce the whole volume of the blade assembly before assembly, thereby facilitating packaging, storage and transportation of the blade assembly. | 09-25-2008 |
Yuh-Ching Wang, Tainan TW
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20100127878 | Alarm Method And System Based On Voice Events, And Building Method On Behavior Trajectory Thereof - Disclosed are an alarm method and system based on voice events, and a building method on behavior trajectory thereof The system comprises a signal sensor, a voice-event detector and notice and alarm element. In the method, voice signals are captured from a remote unit in an environment. The captured voice signals are classified into at least a voice event. As such, an emergent-event notice is automatically transmitted out if one of predefined emergent events is detected. In the building method on behavior trajectory, messages on voice events are continuously recorded. When the number of the recorded voice events reaches a threshold, a behavior trajectory is constructed, in which a behavior consists of two or more voice events or a single voice event. | 05-27-2010 |
Yun-Che Wang, Tainan TW
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20140000185 | COMPOSITE DAMPER | 01-02-2014 |
Yun-Ren Wang, Tainan TW
Patent application number | Description | Published |
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20080254642 | METHOD OF FABRICATING GATE DIELECTRIC LAYER - A method for fabricating gate dielectric layer is provided. First, a sacrificial layer is formed on a substrate. Next, fluorine ions are implanted into the substrate. Then, the sacrificial layer is then removed. Finally, a dielectric layer is formed on the substrate. | 10-16-2008 |
20080318405 | METHOD OF FABRICATING GATE STRUCTURE - A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure. | 12-25-2008 |
Yu-Ting Wang, Tainan TW
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20160027683 | Shallow Trench Isolation Structures in Semiconductor Device and Method for Manufacturing the Same - Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed. | 01-28-2016 |
20160086843 | Shallow Trench Isolation Structures in Semiconductor Device and Method for Manufacturing the Same - Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed. | 03-24-2016 |