Patent application number | Description | Published |
20080250378 | CIRCUIT EMULATION AND DEBUGGING METHOD - A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals. | 10-09-2008 |
20110202894 | Method and Apparatus for Versatile Controllability and Observability in Prototype System - Methods and systems for testing a prototype, the method including receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module. The method further includes, sending, using the first interface component, the configured image to a device. A second interface component may be configured to send timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component. In response to receiving the timing and control information from the second interface component, the verification module may control the device and/or monitor the device state of at least a portion of the user design. | 08-18-2011 |
20130035925 | METHOD AND APPARATUS FOR VERSATILE CONTROLLABILITY AND OBSERVABILITY IN PROTOTYPE SYSTEM - A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation. | 02-07-2013 |
20130117007 | METHOD AND APPARATUS FOR TURNING CUSTOM PROTOTYPE BOARDS INTO CO-SIMULATION, CO-EMULATION SYSTEMS - A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design. Each partitioned circuit in the FPGA device is associated with a verification module for communicating with the controller to control and probe the emulation. A host workstation may be used to link with the controller to support co-simulation or co-emulation of the circuit design. | 05-09-2013 |
20130227509 | PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS - A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards. | 08-29-2013 |
20140157215 | SYSTEM AND METHOD OF EMULATING MULTIPLE CUSTOM PROTOTYPE BOARDS - An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires. | 06-05-2014 |
20140351777 | PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS - A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file. | 11-27-2014 |
Patent application number | Description | Published |
20080221127 | PPAR ACTIVE COMPOUNDS - Compounds are described that are active on at least one of PPARα, PPARδ, and PPARγ, which are useful for therapeutic and/or prophylactic methods involving modulation of at least one of PPARα, PPARδ, and PPARγ. | 09-11-2008 |
20080249137 | PPAR active compounds - Compounds are described that are active on at least one of PPARα, PPARδ, and PPARγ, which are useful for therapeutic and/or prophylactic methods involving modulation of at least one of PPARα, PPARδ, and PPARγ. | 10-09-2008 |
20080255201 | PPAR ACTIVE COMPOUNDS - Compounds are described that are active on at least one of PPARα, PPARδ, and PPARγ, which are useful for therapeutic and/or prophylactic methods involving modulation of at least one of PPARα, PPARδ, and PPARγ. | 10-16-2008 |
20100210036 | PPAR ACTIVE COMPOUNDS - Compounds are described that are active on PPARs, including pan-active compounds. Also described are methods for developing or identifying compounds having a desired selectivity profile. | 08-19-2010 |
20120015966 | PPAR ACTIVE COMPOUNDS - Compounds are described that are active on at least one of PPARα, PPARδ, and PPARγ, which are useful for therapeutic and/or prophylactic methods involving modulation of at least one of PPARα, PPARδ, and PPARγ. | 01-19-2012 |
20120148599 | METHODS AND COMPOSITIONS FOR NEURAL DISEASE IMMUNOTHERAPY - The invention provides antibodies to specific neural proteins and methods of using the same. | 06-14-2012 |
20140286963 | METHODS AND COMPOSITIONS FOR NEURAL DISEASE IMMUNOTHERAPY - The invention provides antibodies to specific neural proteins and methods of using the same. | 09-25-2014 |
Patent application number | Description | Published |
20090247521 | SOLUBLE EPOXIDE HYDROLASE INHIBITORS FOR THE TREATMENT OF ENDOTHELIAL DYSFUNCTION - The present invention generally relates to methods useful for a therapy using a class of urea or amide compounds and related compositions, wherein the compound is a soluble epoxide hydrolase inhibitor, for treating and ameliorating the symptoms of diseases related to endothelial dysfunction. | 10-01-2009 |
20090270452 | USE OF SOLUBLE EPOXIDE HYDROLASE INHIBITORS IN THE TREATMENT OF SMOOTH MUSCLE DISORDERS - Disclosed herein are compounds, compositions, and methods for enhancing smooth muscle function in a subject by administration of soluble epoxide hydrolase inhibitors and for treating subjects with smooth muscle disorders including erectile dysfunction, overactive bladder, uterine contractions and irritable bowel syndrome. | 10-29-2009 |
20100063583 | USE OF SOLUBLE EPOXIDE HYDROLASE INHIBITORS IN THE TREATMENT OF INFLAMMATORY VASCULAR DISEASES - Disclosed herein are compositions and methods for treating inflammatory vascular diseases. Examples of inflammatory vascular disease include, but are not limited to, in-stent stenosis, coronary arterial diseases (CAD), angina, acute myocardial infarction, acute coronary syndrome, chronic heart failure (CHF), peripheral arterial occlusive diseases (PAOD), critical limb ischemia (CLI), cardiac, kidney, liver and intestinal ischemia, renal failure, cardiac hypertrophy, atherosclerosis, abdominal aortic aneurysm, vasculitis, carotid artery stenosis. | 03-11-2010 |