Wang, Hsinchu Hsien
Chien Shun Wang, Hsinchu Hsien TW
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20120127269 | Method and Apparatus for Adjusting 3D Depth of Object and Method for Detecting 3D Depth of Object - A method for adjusting three-dimensional (3D) depth including performing block matching on left-eye/right-eye frames of a stereo video signal to generate a motion vector of a specific object and to obtain 3D depth of the specific object; and adjusting 3D depth of an additive object according to that of the specific object, wherein the additive object is one of a subtitle object, an on screen display (OSD) object or a program guide object. | 05-24-2012 |
Feng-Ho Wang, Hsinchu Hsien TW
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20090071986 | DEVICE FOR DISPENSING A VISCID MATERIAL - A device for dispensing a viscid material includes a supporting body constructed by a carriage. A ball screw is installed within the supporting body. A rod piston is mounted on one end of the ball screw. A transmission module is mounted on a nut of the ball screw. The transmission module is engaged with an actuator controlled by a control circuit device. The control circuit device, which includes a switch and a circuit board, etc, controls the positive and negative rotations and the stop operation of the actuator. A trigger is set up on one side of the supporting body. When the trigger is pressed, the actuator is driven to rotate in the positive direction to drive the ball screw to move forwardly in a stable way. While the trigger is released, a sensor is activated to drive the actuator to rotate in the negative direction. | 03-19-2009 |
Fucheng Wang, Hsinchu Hsien TW
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20080238498 | CLOCK GENERATOR, METHOD FOR GENERATING CLOCK SIGNAL AND FRACTIONAL PHASE LOCK LOOP THEREOF - A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal. | 10-02-2008 |
20090085663 | Transconductor Having High Linearity and Programmable Gain and Mixer using the Same - A mixer having high linearity and an associated transconductor combining programmable gain amplifier and mixer functions are provided. The transconductor includes first and second resistors, a differential amplifier, first and second feedback circuits, and first and second transistors. A differential voltage signal is inputted to first and second input ends of the differential amplifier via the first and second resistors. The first and second feedback circuits are provided between a first output end and the first input end, and a second output end and the second input end of the differential amplifier, respectively. The first output end outputs a first output signal for controlling a first current passing through the first transistor. The second output end outputs a second output signal for controlling a second current passing through the second transistor. The first current and the second current determine a differential current. | 04-02-2009 |
20110051014 | Tuner and Front-end Circuit Thereof - A tuner includes a plurality of paths, and at least one of the paths includes a front-end filter circuit, an amplifier, and a trace filter. The trace filter includes a varactor and an inductor, which are coupled to an output end of the amplifier. Further, the amplifier and the varactor of the tuner are packed in a complementary metal-oxide semiconductor (CMOS) chip. | 03-03-2011 |
20110116586 | Transmitting Apparatus Operative at a Plurality of Different Bands and Associated Method - A transmitting apparatus operative at a plurality of different bands includes at least a modulator, an intermediate frequency (IF) filter, and an offset phase-locked-loop (OPLL). Regardless at which one of the frequency bands the transmitting apparatus operates, a divisor of at least one frequency divider included within the OPLL is fixed, and a signal, which is outputted by a controllable oscillator and received by an offset mixer included within the OPLL, corresponds to a substantially fixed frequency. | 05-19-2011 |
20120105726 | Analog Television Receiver - An analog television (TV) receiver converts a received analog TV signal to a digital TV signal and performs digital demodulation to increase demodulation efficiency. The analog TV receiver includes a radio frequency (RF) turner and an intermediate frequency (IF) circuit. The RF tuner converts the received analog RF TV signal to an analog IF TV signal. The IF circuit includes a converting circuit and a digital demodulator. The converting circuit converts the analog IF TV signal to a digital TV signal. The digital demodulator demodulates the digital TV signal to generate a digital demodulated video signal and a digital demodulated audio signal. | 05-03-2012 |
Fu-Cheng Wang, Hsinchu Hsien TW
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20100302100 | Signal Processing Apparatus for Multi-mode Satellite Positioning System and Method Thereof - A signal processing apparatus for a multi-mode satellite positioning system includes a band-pass filter, a local oscillator circuit, a first mixing circuit, a second mixing circuit, an analog-to-digital converter and a baseband circuit. By properly allocating a local frequency, radio frequency (RF) signals of a Global Positioning System (GPS), a Galileo positioning system and a Global Navigation System (GLONASS) are processed via a single signal path to save hardware cost. | 12-02-2010 |
Jen-Hsing Wang, Hsinchu Hsien TW
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20110002422 | Apparatus for Detecting Digital Video Signal Parameters and Method Thereof - A method for detecting digital video signal parameters detects an integer carrier frequency offset (ICFO), a pilot pattern and a carrier mode of a signal received by an Orthogonal Frequency-Division Multiplexing (OFDM) communication system. The method includes receiving a first OFDM symbol comprising a plurality of first frequency-domain sub-carriers and a second OFDM symbol comprising a plurality of second frequency-domain sub-carriers; generating a plurality of sub-carrier correlation results according to the first frequency-domain sub-carrier and the second frequency-domain sub-carrier; and determining a maximum sub-carrier correlation result from the plurality of sub-carrier correlation results; and outputting an ICFO, a pilot pattern and a carrier mode corresponding to the maximum sub-carrier correlation result. | 01-06-2011 |
20120212674 | Analog TV Signal Receiving Circuit For Reducing Signal Distortion Using Equalizer Configuring Method - An analog television (TV) signal receiving circuit and method and an associated equalizer coefficient configuration apparatus and method are disclosed for correcting a distortion problem occurred in a reception process of an analog TV signal by configuring an equalizer in the analog TV signal receiving circuit. The analog TV signal receiving TV includes a tuner, an analog-to-digital converter (ADC), and a demodulator. The tuner receives an analog radio-frequency (RF) TV signal to generate an analog frequency down conversion signal. The ADC generates a digital frequency down conversion signal according to the analog frequency down conversion signal. The demodulator includes a front-end circuit for generating a digital demodulated signal according to the digital frequency down conversion signal, and an equalizer for generating a digital receiving signal according to the digital demodulated signal. The equalizer includes a plurality of correction coefficients that are generated according to a predetermined rule. | 08-23-2012 |
Jiun-Ren Wang, Hsinchu Hsien TW
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20100283912 | Apparatus for Demodulating Digital Video and Associated Method - An apparatus for demodulating a digital video signal applied to a receiving end of an Orthogonal Frequency-Division Multiplexing (OFDM) communication system is provided. The apparatus receives a plurality of OFDM symbols, and stores a plurality of data sequences in an external memory. The apparatus includes a de-interleaver, that de-interleaves the data sequences to generate a plurality of de-interleaved data sequences; a decoder, coupled to the de-interleaver, that generates a plurality of data streams according to the de-interleaved data sequences; a reconstruction apparatus, coupled to the decoder, that reconstructs the data streams into a transport stream; and a memory interface unit, coupled to the external memory, that accesses the data sequences and the data streams from the external memory. The external memory includes a de-interleaving buffer that stores the data sequence, and a data reconstructing buffer that stores the data streams. | 11-11-2010 |
Ko-Fang Wang, Hsinchu Hsien TW
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20140149704 | MEMORY ACCESS AUTHORITY CONTROL METHOD AND MEMORY MANAGEMENT SYSTEM THEREOF - A memory access authority control method and a memory management system utilizing the method. By partitioning and designating permissible memory access intervals to different service programs in one system, it is ensured that each service program cannot access other service programs' confidential data. Thus, the security of confidential data is guaranteed. | 05-29-2014 |
Ruei-Chin Wang, Hsinchu Hsien TW
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20100122727 | Method for fabricating III-V compound semiconductor solar cell and structure thereof - A method for fabricating a III-V compound semiconductor solar cell includes forming a window layer made of III-V compound material over a top surface of an solar cell structure; forming a periodic array of hole textures of the window layer by using a lithography and etching process; and depositing an anti-reflection coating film to cover the window layer. A III-V compound solar cell structure is also provided to enhance the conversion efficiency of photovoltaic. | 05-20-2010 |
Shih-Chung Wang, Hsinchu Hsien TW
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20100171688 | Driving Method and Apparatus of LCD Panel, and Associated Timing Controller - A timing controller of an LCD panel is provided. The timing controller, for controlling a plurality of source drivers and a plurality of gate drivers of the LCD panel, includes a data processing module for generating a data signal carrying image data and black data, and a control signal generating module for generating a plurality of horizontal start signals, a first gate enable signal and a second gate enable signal. The horizontal start signals are for controlling the inputting of the data signals into the source drivers. The first and second gate enable signals correspond to different enable timings, and are selectively outputted to the gate drivers. | 07-08-2010 |
20110025732 | Timing Controller Utilized in Display Device and Method Thereof - A timing controller utilized in a display device includes an image processing circuit, a luminance adjusting circuit, a data converting circuit and a driving signal generating circuit. The image processing circuit performs image processing on image data of an image signal. The luminance adjusting circuit adjusts luminance of the processed image data according to a luminance characteristic of the display panel of the display device. According to a pixel arrangement of the display panel, the data converting circuit converts the adjusted image data to display data provided to a driving circuit of the display panel. The driving signal generating circuit generates a driving signal to control the driving circuit according to a synchronous signal of the image signal. | 02-03-2011 |
Su-Chun Wang, Hsinchu Hsien TW
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20090316044 | Method and Associated Apparatus for Determining Motion Vectors - A method and an associated apparatus for determining a motion vector are disclosed. The method includes performing block matching for a first block where an interpolated block is located according to the first frame and the second frame to generate a first candidate motion vector of the interpolated block, performing block matching for a second block where the interpolated block is located according to the first frame and the second frame to generate a second candidate motion vector of the interpolated block, and determining a target motion vector of the interpolated block according to either of the first motion vector and the second candidate motion vector. | 12-24-2009 |
20090316799 | Image Processing Circuit and Associated Method - An image processing circuit includes a compression circuit, a plurality of first line buffers, a decompression circuit, and a motion estimation/compensation circuit. The compression circuit receives source image data and compresses the received source image data to generate a compressed image data. The first line buffers, coupled to the compression circuit, sequentially receive the compressed image data and buffer the compressed image data. The decompression circuit, coupled to the first line buffers, decompresses the compressed image data to generate a decompressed image data. The motion estimation/compression circuit, coupled to the decompression circuit, performs motion estimation/compensation according to the decompressed image data. | 12-24-2009 |
20090322957 | Image Processing Method and Related Apparatus for Calculating Target Motion Vector Used for Image Block to be Interpolated - An image processing method includes: detecting a motion vector of a source image block within a first video image to determine a flag value of the source image block, wherein the flag is used for indicating whether image content of the source image block correspondingly includes sight variations; and determining a target motion vector used for an interpolated image block according to the flag value. | 12-31-2009 |
20100238348 | Image Processing Method and Circuit - An image processing circuit includes a de-interlace circuit, a motion interpolation circuit and a frame processing circuit. The image processing circuit receives a first field and a second field respectively from two successive film frames. A plurality of block motion vectors are calculated according to the first field and the second field. A plurality of interpolated frames are calculated according to the first field, the second field and the plurality of motion vectors. | 09-23-2010 |
20110316992 | Image Playback System, Associated Apparatus and Method Thereof - An image playback system displays three-dimensional (3D) content data via a pair of glasses together with a monitor to provide a multiplexing service to a user wearing different types of glasses via a single monitor. For a multiplexing service, the monitor interleaving displays frames of different content data to provide predetermined content data to the user while the glasses shelters other content data. | 12-29-2011 |
Sung-Wen Wang, Hsinchu Hsien TW
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20140185690 | MULTIMEDIA DATA STREAM FORMAT, METADATA GENERATOR, ENCODING METHOD, ENCODING SYSTEM, DECODING METHOD, AND DECODING SYSTEM - By determining multimedia positioning frames, by generating a metadata according to address information of the multimedia positioning frames and the number of multimedia frames following each of the multimedia frames, and by relocating the multimedia frames following each of the multimedia frames, a data storage amount of the metadata can be reduced. Further, when a user wishes to view a specific multimedia frame of a specific time point, the specific multimedia at the specific time point can be decoded and played without having to complete download of all multimedia frames preceding the specific time point. | 07-03-2014 |
Te-Chuan Wang, Hsinchu Hsien TW
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20110026905 | Packet Sequence Restoring Controller and Method Thereof - A packet sequence restoring controller includes a recording device, a memory interface unit and a playback device. The recording device includes a first packet detector, a time stamp inserting unit and a first counting module. The playback device includes a second packet detector, a comparing unit, a time stamp deleting unit and a second counting module. Through the memory interface unit, the recording device and the playback device perform data access with an external memory. By recording arrival time of each packet, a live packet sequence is simulated and restored to optimize play quality of a recorded program. | 02-03-2011 |
20140254999 | DATA ACCESS CONTROL METHOD AND APPARATUS - One embodiment of the present invention discloses a data access method comprising: (a) receiving a plurality of data units consisting of filtered data units and un-filtered data units; (b) filtering the filtered data units; (c) storing the un-filtered data units; (d) recovering the timings of the un-filtered data units stored in the step (c) according to the received timings of the data units received in the step (a); (e) inserting replacement data units to replace the filtered data units, wherein each of the replacement data units has the same timing as each of the filtered data units; and (f) outputting the un-filtered data units and the replacement data units according to the timings of the un-filtered data units and the timing of the replacement data unit. | 09-11-2014 |
Ting-Shing Wang, Hsinchu Hsien TW
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20090096038 | POWER MOSFET ARRAY - A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration. | 04-16-2009 |
Tsai-Sheng Wang, Hsinchu Hsien TW
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20100321380 | Image Processing Method and Associated Apparatus for Rendering Three-dimensional Effect Using Two-dimensional Image - An image processing method for rendering a three-dimensional by transforming a first quadrilateral image to a second quadrilateral image is provided, with at least one of the first and second quadrilateral images being a trapezoidal image. The image processing method includes providing the first quadrilateral image, generating coordinates of four vertices associated with the second quadrilateral image according to the first quadrilateral image and the three-dimensional effect; determining a relative height and a relative width according to a height and a width of the first quadrilateral image and the coordinates of the four vertices; and generating a plurality of pixel values of the second quadrilateral image with reference to a plurality of pixel values of the first quadrilateral image according to the relative height and the relative width. | 12-23-2010 |
20100321381 | Image Processing Method and Associated Apparatus for Rendering Three-dimensional Effect Using Two-dimensional Image - An image processing apparatus is for rendering a three-dimensional (3D) effect by transforming a first quadrilateral image to a second quadrilateral image. The apparatus includes a target image determining unit, a block determining unit and a graphic unit. The target image determining unit generates an outline associated with the second quadrilateral image according to the first quadrilateral image and the 3D effect. The block determining unit divides an area within the outline into a plurality of second blocks and correspondingly determines a plurality of first blocks from the first quadrilateral image. The graphic unit scales image data of the first blocks to respectively generate image data of the second blocks to obtain the second quadrilateral image. | 12-23-2010 |
20100322531 | Image Processing Method and Associated Apparatus - An image processing apparatus and an associated method capable of effectively reducing image artifact at an edge of an image without excessively compromising overall system performance. The method includes calculating an intersection point of an edge of the image and a pixel scan line, estimating a relative ratio of the image within a pixel block corresponding to the intersection point to generate an adjustment parameter, and adjusting a pixel value of the pixel block according to adjustment parameter. | 12-23-2010 |
Wei-Jan Wang, Hsinchu Hsien TW
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20100310081 | Multi-channel Audio Signal Decoding Method and Device - A multi-channel audio signal decoding method and device is provided. The multi-channel audio signal decoding method includes receiving a first multi-channel audio signal; performing a first decoding procedure on the first multi-channel audio signal to generate a second multi-channel audio signal; performing a second decoding procedure on a first single-channel audio data of the second multi-channel audio signal to generate a first single-channel audio signal when the first single-channel audio data belongs to a first classification; and performing a third decoding procedure on a second single-channel audio data of the second multi-channel audio signal to generate a second single-channel audio signal when the second single-channel audio data belongs to a second classification. The number of instructions of the third decoding procedure is less than that of the second decoding procedure. | 12-09-2010 |
Yao-Chi Wang, Hsinchu Hsien TW
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20100134170 | Delay Cell of Ring Oscillator and Associated Method - A delay cell for use in a ring oscillator and associated method is provided. The delay cell includes a differential amplifier, a switched capacitance bank, and a Kvco equalizer. The differential amplifier comprises a differential pair, a first load and a second load. The differential pair includes a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The first load is coupled to the positive output terminal, and the second load is coupled to the negative output terminal. The switched capacitance bank has a plurality of controlled capacitor paths selectively connecting to the positive output terminal or the negative output terminal according to a capacitance controlling signal. The Kvco equalizer has an adjustable current source for providing a current to the Kvco equalizer according to a current controlling signal to compensate currents flowing through the first load and the second load. | 06-03-2010 |
20100141347 | Band Selecting Method Applied to Voltage Controlled Oscillator of Phase Locked Loop Circuit and Associated Apparatus - A band selecting method applied to a voltage controlled oscillator (VCO) of a phase locked loop (PLL) and an associated method is provided. The band selecting method generates an open-loop control voltage according to a temperature signal; inputting the open-loop control voltage into the VCO; switching sequentially between a plurality of frequency bands of the VCO and generating a plurality of voltage controlled signals for the frequency bands; selecting a preferred voltage controlled signal and its corresponding frequency band as an operating band for the PLL. | 06-10-2010 |
20110057696 | Frequency Calibration Apparatus of Phase Locked Loop and Method Thereof - A frequency calibration apparatus, applied to a phase locked loop (PLL), includes a frequency detecting module and a search module. The frequency detecting module includes a first counter, a second counter and a comparing unit. During a monitoring period, the first counter and the second counter respectively generates a first count and a second count. The comparing unit compares the first count with the second count to generate a comparison result indicating at least three situations. The search module selects a frequency curve in response to the comparison result, and calibrates configuration of a voltage controlled oscillator (VCO) according to the frequency curve. | 03-10-2011 |
20110080196 | VCO Control Circuit and Method Thereof, Fast Locking PLL and Method for Fast Locking PLL - A voltage-controlled oscillator (VCO) control circuit, used for controlling a VCO to process phase locking procedure after receiving a frequency locking signal, comprises an operating frequency controller and a judgment unit. The operating frequency controller, coupled to the VCO and the judgment unit, generates one of a first control code and a second control code to the VCO. The judgment unit, coupled to an input end of the VCO, generates a phase locking signal according to a voltage control signal inputted to the VCO. When the operating frequency controller receives the frequency locking signal, the operating frequency controller generates a first control code to control the VCO to switch from a first candidate VCO curve to a second candidate VCO curve. When the operating frequency controller receives the phase locking signal, the operating frequency controller generates a second control code to control the VCO to switch from the second candidate VCO curve to the first candidate VCO curve. | 04-07-2011 |
20110080199 | Bandwidth Control Apparatus for Phase Lock Loop and Method Thereof - A loop bandwidth control apparatus applied to a phase locked loop (PLL) includes a first loop filter module, a second loop filter module, a control module, a first switching module, and a second switching module. The first filter module and the second loop filter module output a first voltage and a second voltage, respectively. The second loop filter module has a bandwidth different from that of the first loop filter module. According to one of the first voltage and the second voltage, the control module generates a bandwidth control signal. According to the bandwidth control signal, the first switching module forms a path between a charge pump and one of the first loop filter module and the second loop filter module, and the second switching module forms a path between a voltage-controlled oscillator (VCO) and one of the first loop filter module and the second loop filter module. | 04-07-2011 |
20110102090 | Phase Locked Loop and Method Thereof - A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO. | 05-05-2011 |
20110122965 | Offset Phase-Locked Loop Transmitter and Method Thereof - An offset phase-locked loop (PLL) transmitter comprises a clock generator that generates a first clock signal; a detector that detects a phase difference between an input data signal and a feedback data signal to generate a control signal; a controlled oscillator, coupled to the detector, that generates an output data signal according to the control signal; a mixer, coupled to the controlled oscillator and the clock generator, that mixes the output data signal according to the first clock signal to generate the feedback data signal; and a control circuit, coupled to the detector and the controlled oscillator, that adjusts the operating frequency curve of the controlled oscillator by one of a first step distance and a second step distance smaller than the first step distance such that the control signal is substantially equal to a predetermined value. | 05-26-2011 |
20140254641 | Circuit and Method for Transmitting or Receiving Signal - A circuit, including a receiving path, for converting a first analog radio frequency (RF) input signal to a digital intermediate frequency (IF) input signal, wherein the first analog RF input signal includes a first signal component conforming to a first wireless transmission standard and a second signal component conforming to a second wireless transmission standard; a first digital down converter, for receiving and processing the digital IF input signal to generate a first digital baseband signal corresponding to the first signal component; a second digital down converter, for receiving and processing the digital IF input signal in order to generate a second digital baseband signal corresponding to the second signal component; a first baseband processing module, for processing the first digital baseband signal according to the first wireless transmission standard; and a second baseband processing module, for processing the second digital baseband signal according to the second wireless transmission standard. | 09-11-2014 |
Yao-Hsin Wang, Hsinchu Hsien TW
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20120016922 | Video Codec and Method thereof - A video codec method is provided, for processing video data processed by a Discrete Cosine Transformation (DCT) operation, comprising: (a) if a transformation matrix having a plurality of coefficients comprises at least one non-integer coefficient among the coefficients, multiplying the transformation matrix by a multiplication factor α to make all coefficients of the transformation matrix integers, (b) estimating a compensation set, (c) performing a Column in Row out IDCT two-dimensional operation on the video data according to the transformation matrix and the compensation set, to obtain a compensated two-dimension operation result, (d) selectively dividing the compensated two-dimension operation result by α | 01-19-2012 |
Yi-Wei Wang, Hsinchu Hsien TW
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20100105433 | Apparatus and Method for Controlling Subscriber Identity Module Card - A Subscriber Identity Module (SIM) card control apparatus applied to a mobile communication device is provided. The mobile communication device has a first SIM card and a second SIM card. The SIM card control apparatus includes a judgment unit, a SIM card controller and a switch device. The judgment unit is used to generate a selection signal according to a to-be-accessed SIM card among the first and the second SIM cards. The SIM card controller transmits signals via a group of signal lines. The switch device is used to selectively connect the group of signal lines to the first SIM card or the second SIM card according to the selection signal. | 04-29-2010 |
Yu Shin Wang, Hsinchu Hsien TW
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20120096209 | Multi peripheral accelerating apparatus - A multi peripheral accelerating apparatus includes a processor device disposed on a main board, a primary memory and a controller disposed on the main board and electrically connected to the processor device for exchanging information with the processor device, a secondary memory disposed on the main board and electrically connected to the controller, and one or more peripherals disposed on the main board and electrically connected to the controller for allowing the information to be transmitted or exchanged from the peripherals to the secondary memory when the processor device is transmitting or exchanging information with the primary memory. | 04-19-2012 |