Patent application number | Description | Published |
20110238910 | DATA STORAGE SYSTEM AND SYNCHRONIZING METHOD FOR CONSISTENCY THEREOF - The invention discloses a data storage system and a synchronizing method for consistency thereof, especially for the data storage system specified in RAID 5 architecture. The data storage system according to the invention includes N storage devices, where N is an integer equal to or larger than 3. The synchronizing method according to the invention performs writing commands for the designated storage device among the N storage devices, and reading commands for the other (N−1) storage devices, to reduce synchronization time of the data storage system. | 09-29-2011 |
20110276759 | DATA STORAGE SYSTEM AND CONTROL METHOD THEREOF - The invention discloses a data storage system and a control method thereof. The data storage system according to the invention includes N groups of storage devices, where N is an integer larger than 1. The invention is to judge if the use information of one of the batches of data satisfies the set of condition thresholds relative to the group of storage devices where said one batch of data is stored, and if NO, to re-allocate said one batch of data to one of the group of storage devices whose condition thresholds are satisfied by the use information of said one batch of data and to update the virtual drive locations of said one batch of data mapping the logical locations of the storage devices. | 11-10-2011 |
20130067171 | DATA STORAGE SYSTEM INCLUDING BACKUP MEMORY AND MANAGING METHOD THEREOF - The invention discloses a data storage system and managing method thereof. The data storage system according to the invention includes N storage devices, a backup memory and a controller where N is a natural number. Each storage device has a respective write cache. Once the data storage system suffers from power failure, the backup memory still reserves data stored therein. The controller receives data transmitted from an application I/O request unit, executes a predetermined operation for the received data to generate data to be written, transmits the data to be written to the write caches of the storage devices, duplicates the data to be written into the backup memory, and labels the duplicated data in the backup memory as being valid in response to a writing confirm message sent from the storage devices. | 03-14-2013 |
Patent application number | Description | Published |
20110007523 | Backlight Module - This present invention discloses a backlight module including a frame and a light guide plate. The frame includes a base plane and a side wall, wherein the side wall is disposed at the edge of the base plane and encloses a disposition space. The side wall includes a first inner surface and an outer surface, wherein a distance between the first inner surface and the outer surface is decreased as the first inner surface comes closer to a bottom of the side wall. The light guide plate is disposed on the base plane and within the disposition space, wherein the first inner surface sinks toward the outer surface and a recessed space is formed between the first inner surface and a lateral side of the light guide plate. | 01-13-2011 |
20120099342 | Complex Circuit Board and Fabrication Method Thereof - A complex circuit board including a printed circuit board assembly (PCBA) and a flexible printed circuit (FPC) for providing driving signals for light sources is disclosed. The PCBA includes a supporting portion and a connecting portion. The light sources are disposed above the supporting portion. The connection portion contacts electrically with a contacting portion of the FPC. The contacting portion of the FPC has a fixing hole. The connecting portion of the PCBA has a fixing portion. Moreover, the FPC has two or more than two first bend portions on the contacting portion. The fixing portion of the PCBA is inserted into the fixing hole of the FPC to complete the complex circuit board without extra attachment units. Therefore, the assembly procedure is simplified to increase throughput and the cost is reduced. | 04-26-2012 |
20130128619 | Backlight Module and Light Source Module Thereof - A backlight module and a light source module thereof are disclosed. The light source module includes a substrate, at least one first light source, and at least one second light source. The substrate includes a first substrate portion and a second substrate portion. The first substrate portion extends along a length direction, and the second substrate portion bends an acute angle corresponding to an extending surface of the first substrate portion. The at least one first light source and the at least one second light source are disposed on the first substrate portion and the second substrate portion respectively. The acute angle is existed between the light-emitting directions of the first light source and the second light source, and the light-emitting directions are parallel to the first substrate portion. | 05-23-2013 |
20140029302 | BACKLIGHT MODULE AND ASSEMBLY METHOD THEREOF - A backlight module includes a light guide plate with at least one light incident surface, and a light source structure arranged at a side of the light guide plate. The light source structure includes a reflection cover and at least one light emitting module. At least one positioning pin is arranged on the reflection cover. The at least one light emitting module is installed on the reflection cover and corresponding to the at least one light incident surface. The at least one light emitting module is fixed on the positioning pin in a rotatable manner, such that the at least one light emitting module can rotate around the positioning pin as an axis when the reflection cover is combined with the light guide plate, so as to allow the at least one light emitting module facing the at least one light incident surface. | 01-30-2014 |
20140109403 | Complex Circuit Board and Fabrication Method Thereof - A complex circuit board including a printed circuit board assembly (PCBA) and a flexible printed circuit (FPC) for providing driving signals for light sources is disclosed. The PCBA includes a supporting portion and a connecting portion. The light sources are disposed above the supporting portion. The connection portion contacts electrically with a contacting portion of the FPC. The contacting portion of the FPC has a fixing hole. The connecting portion of the PCBA has a fixing portion. Moreover, the FPC has two or more than two first bend portions on the contacting portion. The fixing portion of the PCBA is inserted into the fixing hole of the FPC to complete the complex circuit board without extra attachment units. Therefore, the assembly procedure is simplified to increase throughput and the cost is reduced. | 04-24-2014 |
Patent application number | Description | Published |
20080237750 | Silicided metal gate for multi-threshold voltage configuration - A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. | 10-02-2008 |
20090090935 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 04-09-2009 |
20120083076 | Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same - A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described. | 04-05-2012 |
20130120329 | DISPLAY PANEL - A display panel includes a display area, a non-display area, a plurality of signal pads and a passive covering layer. The non-display area is adjacent to the display area. The signal pads are disposed within the non-display area. The passive covering layer is disposed on the display area and extends to cover at least a portion of the non-display area. The passive covering layer has a first thickness within the display area. The passive covering layer has a second thickness within the non-display area. The first thickness is greater than the second thickness. | 05-16-2013 |
20140197456 | Semiconductor Device and Fabricating the Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion. | 07-17-2014 |
20140197457 | FinFET Device and Method of Fabricating Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion of the first fin structure, a semiconductor oxide layer as an outer portion of a middle portion of the first fin structure, the first semiconductor material layer as a center portion of the middle portion of the first fin structure and a second semiconductor material layer as an upper portion of the first fin structure. The semiconductor device also includes a source/drain feature over the substrate in the source/drain region between two adjacent isolation regions and a high-k (HK)/metal gate (MG) stack in the gate region, wrapping over a portion of the first fin structure. | 07-17-2014 |
20140273366 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region. | 09-18-2014 |
Patent application number | Description | Published |
20100141154 | BACKLIGHT MODULE AND METHOD OF CONTROLLING THE LUMINANCE OF THE BACKLIGHT MODULE - A backlight module includes a plurality of light sources, a photo-sensor, and a control circuit. Each light source of the plurality of light sources can operate independently. The photo-sensor detects the luminance of the plurality of light sources to generate a luminance signal. The control circuit drives the plurality of light sources according to the luminance signal. When the backlight module is used in a scanning backlight LCD, the control circuit turns off parts of the plurality of light sources according to a display signal. When all of the plurality of light sources is turned on, the control circuit obtains the luminance signal so as to adjust the luminance of the backlight module according to the luminance signal. | 06-10-2010 |
20110234642 | METHOD FOR INCREASING BACKLIGHT BRIGHTNESS RESOLUTION AND METHOD FOR MODULATING BACKLIGHT BRIGHTNESS - An exemplary method for increasing backlight brightness resolution is adapted for a non-emissive display device which uses a multi-bit brightness modulation data to modulate a backlight brightness thereof. The method includes the steps of: increasing a provision amount of the multi-bit brightness modulation data in a single frame period of the non-emissive display device; and multiplying a frequency of a brightness modulation signal generated according to the multi-bit brightness modulation data, wherein a multiple of the frequency multiplying is associated with the provision amount of the multi-bit brightness modulation data in the single frame period. The present invention also provides a method for modulating backlight brightness, adapted for a non-emissive display device. | 09-29-2011 |
20120032603 | Light Emitting Device and Driving Method thereof - A light emitting device includes a plurality of light emitting modules and a plurality of voltage controlling circuits capable of being independently controlled. Each voltage controlling circuit includes a dynamic voltage controlling module, a current controlling module, and a luminance controlling module. The dynamic voltage controlling module is used for comparing a voltage level at a second terminal of the light emitting module and a voltage level of a reference voltage source, so as to output a first voltage. The current controlling module is used for adjusting a bias current flowing through the light emitting module, according to the first voltage. The luminance controlling module is used for comparing the first voltage with a clock signal, and for generating a pulse width modulation signal according to a result of the comparison, so as to dynamically control a duty cycle of the light emitting module. | 02-09-2012 |
20120229035 | LIGHTING APPARATUS HAVING HIGH OPERATION RELIABILITY AND LIGHTING SYSTEM USING THE SAME - A lighting apparatus having high operation reliability includes a first lighting unit with a first turn-on voltage and a second lighting unit with a second turn-on voltage greater than the first turn-on voltage. The lighting apparatus is put in use for generating output light according to a driving current flowing through the first lighting unit or the second lighting unit. The first lighting unit is capable of generating output light having a first brightness according to the driving current. The second lighting unit, electrically connected in parallel with the first lighting unit, is capable of generating output light having a second brightness according to the driving current. The second brightness is preferably identical to the first brightness. | 09-13-2012 |
Patent application number | Description | Published |
20100182802 | Light Guide Plate and Backlight Module Having V-Cut Structure - A light guide plate having a V-cut structure and a backlight module are disclosed. The light guide plate comprises straight-striped V-cut structure sets and a base plate having a light-entering side. The straight-striped V-cut structure sets are formed on a surface of the base plate adjacent to the light-entering side, wherein each straight-striped V-cut structure set is composed of at least one V-cut element, each V-cut element having a first base angle and a second base angle formed between its respective two inclined surfaces and a horizontal surface of the base plate. The first base angle is located closer to the light-entering side than the second base angle is, and is smaller than or equal to the second base angle. The straight-striped V-cut structure sets have a plurality of second average angle values which are gradually decreased from the light-entering side to a central position of the base plate. | 07-22-2010 |
20110128757 | Backlight Module Having a Light Guide Plate with Prismatic Structures and Manufacturing Method Thereof - A backlight module having a light guide plate with prismatic structures and a manufacturing method thereof are provided. The backlight module includes a light guide plate, a brightness enhancement film, and a light source module. The light guide plate includes a first surface and a second surface opposite to each other. The first surface has prismatic structures disposed side by side thereon. Each of the prismatic structures includes a first slope and a second slope being adjacent to each other and having an included angle with respect to the first surface, respectively. The included angles are equivalent. The brightness enhancement film includes a third surface and a fourth surface opposite to each other. The third surface faces the second surface. The fourth surface has prisms disposed side by side thereon along the extending direction of the prismatic structure. The brightness enhancement film has an optimum incident angle associated with an angle of the prism and corresponding to the included angles. The light source module is disposed beside the light guide plate along the extending direction of the prismatic structure. | 06-02-2011 |
20130082981 | OPTICAL TOUCH SYSTEM AND OPTICAL TOUCH DEVICE AND OPTICAL TOUCH METHOD - An optical touch system includes a display unit, a touch operation unit, and a data processing unit. The display unit is configured for displaying at least a general image frame and displaying a specific pattern frame alternately with the at least a general image frame. The touch operation unit is configured for scanning a part of the specific pattern frame and capturing image data corresponding to the part of the specific pattern frame for transmission. The data processing unit is configured for translating the image data into a coordinate position. Moreover, an optical touch device and an optical touch method also are provided. | 04-04-2013 |
20140185273 | Backlight Module for Light Field Adjustment - A backlight module for light field adjustment includes a light source module, an optical structure layer, a first prism film, and a second prism film. The light source module has a light exit surface, and the light exit surface has a normal direction. The optical structure layer is disposed on the light exit surface and has a plurality of microstructures convex toward the light exit surface, wherein the microstructures guide light generated from the light exit surface away from the normal direction. The first prism film is disposed on one side of the optical structure layer opposite to the light source module and has a plurality of first prisms extending along a first direction, wherein the first prisms converge light leaving from the optical structure layer toward the normal direction on a cross section vertical to the first direction. | 07-03-2014 |
Patent application number | Description | Published |
20090064784 | MICROMACHINED SENSORS - The present invention provides a micromachined sensor. The micromachined sensor includes a proof mass movable with respect to a substrate. The proof mass includes a first portion, a second portion separated from the first portion and a third portion connecting the first portion to the second portion. A frame is positioned on the substrate and encloses the proof mass. A plurality of springs connects the proof mass to the frame. A plurality of first and second electrodes extends from the frame. A plurality of third electrodes extends from the first portion of the proof mass and is interleaved with the first electrodes. A plurality of fourth electrodes extends from the second portion of the proof mass and is interleaved with the second electrodes. A first support beam extends from the frame to the area between the first and second portions of the proof mass. A plurality of seventh and eighth electrodes extends from the first support beam. A plurality of fifth electrodes extends from the first portion of the proof mass and is interleaved with the seventh electrodes. A plurality of sixth electrodes extends from the second portion of the proof mass and is interleaved with the eighth electrodes | 03-12-2009 |
20100289065 | MEMS INTEGRATED CHIP WITH CROSS-AREA INTERCONNECTION - The present invention discloses a MEMS (Micro-Electro-Mechanical System) integrated chip with cross-area interconnection, comprising: a substrate; a MEMS device area on the substrate; a microelectronic device area on the substrate; a guard ring separating the MEMS device area and the microelectronic device area; and a conductive layer on the surface of the substrate below the guard ring, or a well in the substrate below the guard ring, as a cross-area interconnection electrically connecting the MEMS device area and the microelectronic device area. | 11-18-2010 |
20110126623 | OPTICAL DETECTION METHOD AND OPTICAL MEMS DETECTOR, AND METHOD FOR MAKING MEMS DETECTOR - The present invention discloses an optical MEMS detector, comprising: a substrate; at least one photo diode in a region within the substrate; an isolation wall above the substrate and surrounding the photo diode region; and at least one movable part having an opening for light to pass through and reach the photo diode, wherein when the at least one movable part is moved, an amount of light reaching the photo diode is changed. | 06-02-2011 |
20110127620 | MEMS INTEGRATED CHIP AND METHOD FOR MAKING SAME - The present invention discloses a MEMS (Micro-Electro-Mechanical System) chip and a method for making the MEMS chip. The MEMS chip comprises: a first substrate having a first surface and a second surface opposing each other; a microelectronic device area on the first surface; a first MEMS device area on the second surface; and a conductive interconnection structure electrically connecting the microelectronic device area and the first MEMS device area. | 06-02-2011 |
20110162453 | MASS FOR USE IN A MICRO-ELECTRO-MECHANICAL-SYSTEM SENSOR AND 3-DIMENSIONAL MICRO-ELECTRO-MECHANICAL-SYSTEM SENSOR USING SAME - A 3-dimensional MEMS sensor, comprising: a first axis fixed electrode; a second axis fixed electrode; a third axis fixed electrode; a movable electrode frame including a first axis movable electrode, a second axis movable electrode, a third axis movable electrode, and a connection part connecting the movable electrodes, wherein the first axis movable electrode and the first axis fixed electrode form a first capacitor along the first axis, the second axis movable electrode and the second axis fixed electrode form a second capacitor along the second axis, and the third axis movable electrode and the third axis fixed electrode form a third capacitor along the third axis, the connection part including a center mass, wherein the center mass is at least connected with one of the first, second and third axis movable electrodes, and has an outer periphery and a first interconnecting segment connecting at least two adjacent sides of the outer periphery; at least one spring connecting with the movable electrode frame; and at least one anchor connecting with the spring, wherein the first, second and third axes are not parallel to one another such that they define a 3-dimensional coordinate system. | 07-07-2011 |
20110236805 | MEMS lithography mask with improved tungsten deposition topography and method for the same - The present invention discloses a MEMS lithography mask with improved tungsten deposition topography and a method for making the same. The MEMS lithography mask includes: a pattern including at least two sections forming a conjunction with each other, each of the at least two sections having a width not less than a minimum width, the conjunction having a center and a plurality of corners, wherein at least one of the corners is inwardly recessed to reduce a width of the conjunction, the sections being for defining trenches on a substrate to be filled with tungsten as apart of a MEMS device, whereby the lowest height of the tungsten surface is not lower than 80% of the trench height. | 09-29-2011 |
20110298136 | MEMS INTEGRATED CHIP WITH CROSS-AREA INTERCONNECTION - The present invention discloses a MEMS (Micro-Electro-Mechanical System) integrated chip with cross-area interconnection, comprising: a substrate; a MEMS device area on the substrate; a microelectronic device area on the substrate; a guard ring separating the MEMS device area and the microelectronic device area; and a conductive layer on the surface of the substrate below the guard ring, or a well in the substrate below the guard ring, as a cross-area interconnection electrically connecting the MEMS device area and the microelectronic device area. | 12-08-2011 |
20110304009 | MEMS INTEGRATED CHIP WITH CROSS-AREA INTERCONNECTION - The present invention discloses a MEMS (Micro-Electro-Mechanical System) integrated chip with cross-area interconnection, comprising: a substrate; a MEMS device area on the substrate; a microelectronic device area on the substrate; a guard ring separating the MEMS device area and the microelectronic device area; and a conductive layer on the surface of the substrate below the guard ring, or a well in the substrate below the guard ring, as a cross-area interconnection electrically connecting the MEMS device area and the microelectronic device area. | 12-15-2011 |
20120075422 | 3D INFORMATION GENERATOR FOR USE IN INTERACTIVE INTERFACE AND METHOD FOR 3D INFORMATION GENERATION - The present invention discloses a 3D information generator for use in an interactive interface. The 3D information generator includes: a MEMS light beam generator having at least one light source for providing a dot light beam and a MEMS mirror for projecting a movable scanning light beam according to the dot light beam to an object; an image sensor for sensing an image of the object to generate a 2D image information; and a processor for generating a distance information by triangulation method according to a reflection result of the scanning light beam scanning on the object, wherein the distance information is combined with the 2D image information to generate a 3D information. | 03-29-2012 |
20120235255 | MEMS acoustic pressure sensor device and method for making same - The present invention discloses a Micro-Electro-Mechanical System (MEMS) acoustic pressure sensor device and a method for making same. The MEMS device includes: a substrate; a fixed electrode provided on the substrate; and a multilayer structure, which includes multiple metal layers and multiple metal plugs, wherein the multiple metal layers are connected by the multiple metal plugs. A cavity is formed between the multilayer structure and the fixed electrode. Each metal layer in the multilayer structure includes multiple metal sections. The multiple metal sections of one metal layer and those of at least another metal layer are staggered to form a substantially blanket surface as viewed from a moving direction of an acoustic wave. | 09-20-2012 |
20120261775 | MEMS microphone device and method for making same - The present invention discloses a MEMS microphone device and its manufacturing method. The MEMS microphone device includes: a substrate including a first cavity; a MEMS device region above the substrate, wherein the MEMS device region includes a metal layer, a via layer, an insulating material region and a second cavity; a mask layer above the MEMS device region; a first lid having at least one opening communicating with the second cavity, the first lid being fixed above the mask layer; and a second lid fixed under the substrate. | 10-18-2012 |
20130313662 | MEMS MICROPHONE DEVICE AND METHOD FOR MAKING SAME - The present invention discloses a MEMS microphone device and its manufacturing method. The MEMS microphone device includes: a substrate including a first cavity; a MEMS device region above the substrate, wherein the MEMS device region includes a metal layer, a via layer, an insulating material region and a second cavity; a mask layer above the MEMS device region; a first lid having at least one opening communicating with the second cavity, the first lid being fixed above the mask layer; and a second lid fixed under the substrate. | 11-28-2013 |
20130334623 | MEMS Sensing Device and Method for the Same - The present invention discloses a MEMS sensing device which comprises a substrate, a MEMS device region, a film, an adhesive layer, a cover, at least one opening, and a plurality of leads. The substrate has a first surface and a second surface opposite the first surface. The MEMS device region is on the first surface, and includes a chamber. The film is overlaid on the MEMS device region to seal the chamber as a sealed space. The cover is mounted on the MEMS device region and adhered by the adhesive layer. The opening is on the cover or the adhesive layer, allowing the pressure of the air outside the device to pressure the film. The leads are electrically connected to the MEMS device region, and extend to the second surface. | 12-19-2013 |
Patent application number | Description | Published |
20100112811 | METHOD FOR PATTERNING A METAL GATE - The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer. | 05-06-2010 |
20150086910 | METHOD FOR MAKING A LITHOGRAPHY MASK - A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout. | 03-26-2015 |
Patent application number | Description | Published |
20090244491 | PROJECTOR AND LAMP MODULE LATERALLY EXTRACTED OUT - A projector includes a case, an optical engine, a lamp module, and a centrifugal fan. The optical engine, the lamp module, and the centrifugal fan are disposed in the case. The case has a side cover. The lamp module is disposed adjacent to the side cover to generate heat as well as light which is modulated by the optical engine into an image light. The centrifugal fan is disposed adjacent to the lamp module, impelling air into the lamp module from a side and out from the rear to dissipate heat from the lamp module. | 10-01-2009 |
20090262315 | PROJECTOR AND MODULE OF INTEGRATION ROD - A module of integration rod can be assembled on an optical engine base of a projector. The module of integration rod includes a holder, an integration rod, a cover, at least one elastic element, at least one fastening screw, and at least one adjusting screw. The holder has an accommodating space. The integration rod is inserted in the accommodating space. The integration rod and the holder are disposed on the optical engine base. The cover is disposed on the holder to locate the holder between the cover and the optical engine base. The elastic element is disposed between the holder and the optical engine base. The fastening screw passes through the cover from a first side of the cover and is fastened on the optical engine base. The adjusting screw is fastened on the cover from the first side of the cover and is suitable to lean on the holder. | 10-22-2009 |
20100073581 | PROJECTION SYSTEM AND EXPANSION MODULE - A projection system and an expansion module adapted to a projector are provided. The projection system includes a projector and an expansion module. The expansion module includes a housing, a logic circuit, and an output port. The logic circuit is disposed in the housing to control an operation of the expansion module. The output port is disposed in the housing and coupled to the logic circuit. The output port is connected to an input port of the projector and outputs a data stream to the input port, such that the projector generates an image and projects the image according to the data stream. | 03-25-2010 |
20110222216 | HANDHELD ELECTRONIC DEVICE - A handheld electronic device includes a main body and a cover. The main body has a bottom surface and a side surface adjacent to each other. A strap hole is formed in the side surface of the main body. A receiving slot and an observing opening are formed in the bottom surface. The observing opening is located at an edge of the bottom surface and is aligned and communicates with the strap hole. The cover is detachably disposed on the bottom surface to cover the receiving slot and the observing opening. | 09-15-2011 |
20110244728 | UNIVERSAL SERIAL BUS CONNECTOR AND ADAPTOR OF THE CONNECTOR - A USB connector includes a body and first to fifth pins. The body has the same size as a type A USB connector. The first to fifth pins are disposed in the body. The first pin is adapted to be electrically connected to a power voltage. The second and the third pins are capable of transmitting a differential data signal. The fifth pin is adapted to be electrically connected to a reference voltage. The fifth pin and the fourth pin are a predetermined distance apart, so that the fourth pin is connected to the fifth pin via a ground pin of the four pins of a type A USB connector when the type A USB connector is connected to the USB connector. Furthermore, an adaptor of the USB connector is also provided. | 10-06-2011 |
Patent application number | Description | Published |
20110148859 | METHOD OF DETERMINING POINTING OBJECT POSITION FOR THREE-DIMENSIONAL INTERACTIVE SYSTEM - An exemplary method of determining a pointing object position for three-dimensional interactive system, adapted for an interaction between a pointing object and a three-dimensional interaction display with embedded optical sensors. The method includes the steps of: acquiring a two-dimensional detected light intensity distribution caused by the pointing object acting on the three-dimensional interaction display; obtaining two light-shading intensity maximum values according to the two-dimensional detected light intensity distribution; and determining a one-dimensional positional information of the pointing object on a distance direction of the pointing object relative to the three-dimensional interaction display by use of the positional distance between the two light-shading intensity maximum values. | 06-23-2011 |
20120105321 | METHOD UTILIZED IN THREE-DIMENSIONAL POINTING SYSTEM - A method utilized in a three-dimensional pointing system is provided according to the present invention. The three-dimensional pointing system includes a pointing device, a sensor array, and a display panel, wherein the sensor array is embedded within the display panel. The pointing device projects a pointer onto the display panel to form a projection image, and the sensor array accordingly generates a sensed image which includes the projection image. The method determines at least one space status information based on the sensed image. | 05-03-2012 |
20130044093 | DISPLAY AND METHOD OF DETERMINING A POSITION OF AN OBJECT APPLIED TO A THREE-DIMENSIONAL INTERACTIVE DISPLAY - A display includes a backlight source, display panel, first light source, and controller. The display panel includes a sensor array for sensing first reflection light generated from an object reflecting first detection light. The first detection light is generated by the backlight source for locating a coordinate of a projection point of the object on the display panel. The first light source is disposed in a first side of the display panel, for repeatedly transmitting second detection light of different transmitting angles to the object at different time to generate a second reflection light. The second reflection light is sensed by the sensor array. The controller is for performing a corresponding operation according to a transmitting angle of the first light source and the coordinate of the projection point when brightness value of the reflective light is substantially greater than a predict value. | 02-21-2013 |
20130155057 | THREE-DIMENSIONAL INTERACTIVE DISPLAY APPARATUS AND OPERATION METHOD USING THE SAME - A three-dimensional interactive display apparatus includes a display panel, two light source generators and a processing circuit. The two light source generator generators are configured to respectively emit two lights according to a predetermined sequence, and emission periods of the two second light source generators are configured to not overlap. The processing circuit is configured to sequentially obtain a plurality of images through sensing the two lights by a plurality light sensors, determine the corresponding light source generator of each one image according to the predetermined sequence, and further determine position information of the corresponding light source generator according to image information of the one image. An operation method of the aforementioned three-dimensional interactive display apparatus is also provided. | 06-20-2013 |
20130169596 | THREE-DIMENSIONAL INTERACTION DISPLAY AND OPERATION METHOD THEREOF - A three-dimensional interaction display includes a display panel having a plurality of light sensing devices, a first light emitting device, a second light emitting device, and a processing circuit. The first light emitting device includes a first light emitting surface including a first pattern, and the first pattern includes a first shape boundary having a first total length. The second light emitting device includes a second light emitting surface including a second pattern, and the second pattern includes a second shape boundary having a second total length. The processing circuit is electrically connected to the plurality of light sensing devices for processing an image obtained by the light sensing devices, calculating the total length of the shape boundary of each of the patterns shown in the obtained image, and determining the corresponding light emitting device according to the total length of the shape boundary of each of the patterns. | 07-04-2013 |
Patent application number | Description | Published |
20090085126 | Hybrid metal fully silicided (FUSI) gate - A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer. | 04-02-2009 |
20090280632 | MOSFETS Having Stacked Metal Gate Electrodes and Method - MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate. | 11-12-2009 |
20100221878 | Hybrid Metal Fully Silicided (FUSI) Gate - A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer. | 09-02-2010 |
Patent application number | Description | Published |
20080261394 | Method for fabricating semiconductor device with silicided gate - A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure. | 10-23-2008 |
20090020757 | Flash Anneal for a PAI, NiSi Process - A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impurity ions have been implanted. A PAI process generates an amorphous layer within the source and drain region. A metal is deposited and is reacted to create a silicide within the amorphous layer, without exacerbating existing defects. Conductivity of the source and drain region is then recovered by flash annealing the substrate. | 01-22-2009 |
20100273324 | METHODS OF MANUFACTURING METAL-SILICIDE FEATURES - A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed. | 10-28-2010 |
20100314698 | METHODS OF MANUFACTURING METAL-SILICIDE FEATURES - A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed. | 12-16-2010 |
Patent application number | Description | Published |
20110228894 | SHIFT REGISTER CIRCUIT AND GATE DRIVING CIRCUIT - An exemplary shift register circuit includes a shift register, a first switching circuit and a second switching circuit. The shift register has a start pulse signal input terminal and a start pulse signal output terminal. The first switching circuit includes a first input switch unit and a second output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. The second switching circuit includes a second input switch unit and a first output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. Moreover, on-off states of the first input and first output switch units are opposite to on-off states of the second input and second output switch units. Moreover, a gate driving circuit using the above-mentioned shift register and switching circuits also is provided. | 09-22-2011 |
20120093276 | GATE-ON ARRAY SHIFT REGISTER - A gate-on array shift register includes a signal-input unit, a control transistor and at least three stable modules. The signal-input unit receives and outputs a previous-stage output signal. The control terminal of the control transistor is electrically coupled to the signal-input unit for receiving the previous-stage output signal. The control transistor outputs corresponding output signal on output terminal of the shift register according to the previous-stage output signal. Each of the stable modules is electrically coupled to the control terminal of the control transistor and the output terminal of the shift register to stabilize voltage of the terminals. | 04-19-2012 |
20140197428 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes an array substrate, an opposite substrate, and at least one closed sealing element. The array substrate has a first through hole, and the array substrate includes a plurality of pixel units, a plurality of scan lines, and a plurality of data lines. The scan lines are electrically connected to the pixel units. The data lines intersect with the scan lines, and the data lines are electrically connected to the corresponding pixel units. The opposite substrate is disposed opposite to the array substrate, and the opposite substrate has a second through hole. The closed sealing element is disposed between the array substrate and the opposite substrate, and the closed sealing element has a third through hole. The first through hole, the second through hole, and the third through hole form an opening. | 07-17-2014 |
Patent application number | Description | Published |
20090207662 | Multi-Transistor Non-Volatile Memory Element - The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates. | 08-20-2009 |
20100008141 | Strap-Contact Scheme for Compact Array of Memory Cells - A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrative embodiment, a strap-contact corridor is spaced at n bit-line intervals (n>1) across the array. The strap-contact corridor comprises strap-contact cells, which provide electrical interconnection between control-gate lines, erase gate lines, common-source lines, and word-lines and their respective straps. | 01-14-2010 |
20110267897 | Non-Volatile Memory Cells Formed in Back-End-of-Line Processes - A method for forming and operating an integrated circuit, including providing a substrate; forming a bottom electrode over the substrate, wherein the bottom electrode is in or over a lowest metallization layer over the substrate; forming a blocking layer over the substrate; forming a charge-trapping layer over the blocking layer; forming an insulation layer over the charge-trapping layer; forming a control gate over the insulation layer; forming a tunneling layer over the control gate; and forming a top electrode over the tunneling layer. | 11-03-2011 |
20110286284 | MULTI-TRANSISTOR NON-VOLATILE MEMORY ELEMENT - The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates. | 11-24-2011 |
20140239418 | Semiconductor Dielectric Interface and Gate Stack - A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of the substrate; and depositing a dielectric layer above the termination layer, the depositing configured to not disrupt the termination layer. The forming of the termination layer may be configured to produce the termination layer having a single layer of oxygen atoms between the substrate and the dielectric layer. | 08-28-2014 |
20140353771 | Semiconductor Dielectric Interface and Gate Stack - A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer. | 12-04-2014 |
Patent application number | Description | Published |
20080238346 | Substrate Splitting Apparatus and a Method for Splitting a Substrate - A substrate splitting apparatus and a method for splitting a substrate using the substrate splitting apparatus are provided. The substrate splitting apparatus includes a servo motor, a transmission device, a substrate breaking bar, and a stage. One end of the transmission is directly or indirectly coupled to the servo motor while the other end is coupled with the breaking bar. The stage has a load-lock surface and the load-lock surface faces the breaking bar. The servo motor drives the transmission device to move the breaking bar toward the load-lock surface. A substrate with a pre-crack on the bottom is disposed on the load-lock surface. The servo motor drives the substrate breaking bar to move towards or away from the pre-crack. The method of splitting includes the following steps: forming a pre-crack on the substrate; controlling the servo motor to drive the breaking bar to move towards the substrate; and controlling the breaking bar to press the substrate at the pre-crack. | 10-02-2008 |
20090258565 | Method for Manufacturing Display Panel within Substrates having Different Thickness - The present invention provides a method for manufacturing display panel with substrates having different thickness. The display panel manufacturing method includes assembling a first substrate and a second substrate, positioning the anti-etching layer on the outer surface of the first substrate and etching the substrates at the first etching process. Because the anti-etching layer is disposed on the first substrate, the first substrate is protected by the anti-etching layer from being etched or later etched. Simultaneously, the second substrate is etched to reduce its thickness in order to adjust the thickness difference between the first substrate and the second substrate. | 10-15-2009 |
20090268130 | Display panel using laser cutting technology and the mother substrate thereof - A display panel using laser cutting technology and a mother substrate thereof are provided. The display panel comprises two base plates opposite to each other, a sealant and a buffering metal layer. The sealant is disposed between the two base plates. The buffering metal layer formed on the inside surface of at least one of the two base plates is disposed along the sealant. At least a portion of the buffering metal layer is positioned outside the sealant. There is a first distance between the rim of the buffering metal layer and the edge of the base plate. | 10-29-2009 |
20100045921 | Display Motherboard and Display Panel - A display motherboard includes a first substrate, a second substrate, a plurality of cutting lines, and at least one photo supporting member. The second substrate is opposite the first substrate. The cutting lines are disposed on the first substrate and the second substrate, wherein the cutting lines separate the first substrate and the second substrate into at least one display panel. The photo supporting member is located between the first substrate and the second substrate, wherein the photo supporting member overlaps the cutting lines, and the photo supporting member has a bar shape surrounding the display panel. | 02-25-2010 |
20110025940 | DISPLAY PANEL AND METHOD FOR NARROWING EDGES AND INCREASING EDGE STRENGTH THEREOF - An edge narrowing method for a display panel is disclosed. The display panel includes a first substrate, a second substrate, a sealant and a light-shielding area. The sealant is disposed between the first substrate and the second substrate. The light-shielding area is disposed between the first substrate and the sealant. The method includes the steps of providing the display panel, a grinding apparatus and a polishing apparatus; tilting the display panel so that the first substrate and a grinding member of the grinding apparatus have a first grinding angle therebetween; grinding the first substrate and the light-shielding area with the grinding apparatus while the display panel is tilted at the first grinding angle, thereby forming a first grinding end surface; stopping grinding of the first substrate and the light-shielding area when the width of the light-shielding area is between 0.35 and 1 mm; and polishing the first grinding end surface with the polishing apparatus to form a first end surface. | 02-03-2011 |
20140370240 | DISPLAY PANEL AND METHOD FOR NARROWING EDGES AND INCREASING EDGE STRENGTH THEREOF - An edge narrowing method for a display panel is disclosed. The method includes the steps of providing the display panel, a grinding apparatus and a polishing apparatus; tilting the display panel so that the first substrate and a grinding member of the grinding apparatus have a first grinding angle therebetween; grinding the first substrate and the light-shielding area with the grinding apparatus while the display panel is tilted at the first grinding angle, thereby forming a first grinding end surface; stopping grinding of the first substrate and the light-shielding area when the width of the light-shielding area is between 0.35 and 1 mm; and polishing the first grinding end surface with the polishing apparatus to form a first end surface. | 12-18-2014 |
Patent application number | Description | Published |
20080237746 | Gated diode with non-planar source region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage. | 10-02-2008 |
20100237441 | Gated Diode with Non-Planar Source Region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage. | 09-23-2010 |
20130277750 | Semiconductor Device and Method for Forming Same - A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors. | 10-24-2013 |
20130299944 | Methods and Apparatus for Bipolar Junction Transistors and Resistors - Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer. | 11-14-2013 |
20140327086 | Semiconductor Device and Method for Forming Same - A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors. | 11-06-2014 |
20150035012 | Methods and Apparatus for Bipolar Junction Transistors and Resistors - Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer. | 02-05-2015 |
Patent application number | Description | Published |
20090195752 | Projector and digital micor-mirror device module - A projector includes a light source system for providing an incident light, a digital micro-mirror device (DMD) module and a projection lens. The digital micro-mirror device module is disposed in the light path of the incident light for receiving and modulating the incident light before reflecting the incident light to form an image light. The projection lens is to receive and project the image light to form an image. The DMD module includes an active area plane and a cover glass. The active area plane has plural digital micro-mirror elements for reflecting the incident light to form an image light. The cover glass is disposed in the light paths of the incident light and image light, and has a first transparent surface and a second transparent surface. An included angle is formed between the extension direction of the first transparent surface and the extension direction of the active area plane. | 08-06-2009 |
20100283977 | ILLUMINATION SYSTEM AND ILLUMINATION CONTROL METHOD - An illumination system adapted to a projection apparatus is provided, including a light source module, a light color modulating module, and a control unit. The light color modulating module has a plurality of light color modulating units and is disposed in a transmission path of a light beam. The light color modulating module is capable of moving so that the light color modulating units move into the illumination region of the light beam. When the control unit determines that a boundary of any two adjacent light color modulating units has moved into the illumination region of the light beam, the control unit switches the light source module to an off-state. When the boundary of any two adjacent light color modulating units has moved away from the illumination region of the light beam, the control unit switches the light source module to an on-state. An illumination control method is also provided. | 11-11-2010 |
20110115993 | LIQUID CRYSTAL GLASSES, PROJECTION DISPLAY SYSTEM AND CONTROL METHOD THEREOF - A projection display system includes a glasses system, a driving unit and a projection apparatus. The driving unit is electrically connected to the glasses system for repeatedly applying or removing a voltage to/from the glasses system. The projection apparatus includes an illumination system and a color wheel. The color wheel is in a transmission path of a light beam provided by the illumination system. The color wheel has a compensation zone and a plurality of color zones. When the color wheel is rotated, the compensation zone and the color zones sequentially pass through the light beam. The compensation zone has first, second and third sub compensation zones. A time for the first sub compensation zone passing through the light beam is substantially equal to a time for the third sub compensation zone passing through the light beam. A liquid crystal glasses and a control method are also provided. | 05-19-2011 |
20110242495 | LIGHT SOURCE MODULE AND PROJECTION APPARATUS - A light source module and a projection apparatus are provided. The light source module includes a first light-emitting device, a wavelength conversion device, a second light-emitting device and a light combination device. The first light-emitting device emits an exciting beam. The wavelength conversion device is disposed on a transmission path of the exciting beam, and converts the exciting beam into a first color beam. The wavelength conversion device is suitable for moving, so that the exciting beam illuminates into different positions of the wavelength conversion device at different time. The second light-emitting device emits a second color beam. Colors of the first color beam and the second color beam are different. The light combination device is disposed on transmission paths of the first color beam and the second color beam, and combines the first color beam and the second color beam. | 10-06-2011 |
20120099082 | ILLUMINATION APPARATUS AND PROJECTION APPARATUS - An illumination apparatus including a first light emitting device, a first phosphor layer, a second light emitting device and a second phosphor layer and a beam combining element is provided. The first light emitting device is capable of providing a first light beam and the first phosphor layer is disposed on the transmission path of the first light beam. The second light emitting device is disposed opposite to the first light emitting device and for providing a second light beam, wherein the second phosphor layer is disposed on the transmission path of the second light beam. The beam combining element is disposed between the first phosphor layer and the second phosphor layer. In addition, the invention also provides a projection apparatus. | 04-26-2012 |
20130265801 | DISPLAY AND PROJECTION DEVICE - A display and projection device includes a first shell, a display module, a projection light valve, and a projection lens. The first shell has a display surface and a non-display surface. The display module is disposed within the first shell. The display surface of the first shell exposes the display module. The projection light valve is disposed within the first shell and capable of emitting an image light beam, and the non-display surface of the first shell exposes the projection light valve. The projection lens is disposed outside of the first shell and is located at a transmission path of the image light beam. The projection lens is detachably connected with the non-display surface of the first shell. Moreover, a projection device including a Fresnel lens is also provided. | 10-10-2013 |
20140376261 | BACK LIGHT MODULE - A back light module includes a light guide plate, at least one first light source, at least one second light source and at least one first reflection element. The light guide plate includes a first light incident surface, a second light incident surface opposite to the first light incident surface, a light emitting surface, and a bottom surface opposite to the light emitting surface. The first light source is disposed beside the first light incident surface and suitable to provide a first non-collimated light beam to the first light incident surface. The second light source is disposed beside the second light incident surface and suitable to provide a first collimated light beam to the second light incident surface. The first reflection element is disposed beside the first light incident surface to reflect the first collimated light beam emitted so as to make the first collimated light beam diverge. | 12-25-2014 |
Patent application number | Description | Published |
20100296016 | ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - An active array substrate, a liquid crystal display panel and a method for manufacturing the active array substrate are provided. The active array substrate includes a base, scan lines, data lines and gate tracking lines disposed on the base. Each of the gate tracking lines has first portions, auxiliary portions and junction portions, wherein the junction portion and the first portion are formed in different layers. One of the junction portions is electrically connected with corresponding one of the first portions. | 11-25-2010 |
20110122052 | DISPLAY DEVICE - A display device includes a plurality of gate lines, data lines, first external gate tracking lines, and second external gate tracking lines. The first external gate tracking lines are substantially disposed in a border region of a substrate, and electrically connected with corresponding gate lines. The second external gate tracking lines are substantially disposed in the border region of the substrate, and electrically connected with corresponding gate lines. One of the first external gate tracking lines and a corresponding second external gate tracking line at least partially overlap with each other. | 05-26-2011 |
20120169956 | LCD PANEL CAPABLE OF COMPENSATING THE FEED-THROUGH VOLTAGE - An LCD panel transmits the display data to sub-pixels in a zigzag pattern through a data line. The variation of the feed-through voltages of the sub-pixels may be modified by adjusting the ratios of the channel widths and the channel lengths of the TFTs in the sub-pixels to some predetermined ratios, or by adjusting the compensation capacitance to the coupling capacitance of the TFTs of the sub-pixels. | 07-05-2012 |
20130286310 | LCD PANEL CAPABLE OF COMPENSATING THE FEED-THROUGH VOLTAGE - An LCD panel transmits the display data to sub-pixels in a zigzag pattern through a data line. The variation of the feed-through voltages of the sub-pixels may be modified by adjusting the ratios of the channel widths and the channel lengths of the TFTs in the sub-pixels to some predetermined ratios, or by adjusting the compensation capacitance to the coupling capacitance of the TFTs of the sub-pixels. | 10-31-2013 |
20130309829 | Method of Forming a Semiconductor Device - A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film. | 11-21-2013 |
20140151762 | Semiconductor Device and Method of Forming the Same - A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film. | 06-05-2014 |
20140264575 | MECHANISMS FOR DOPING LIGHTLY-DOPED-DRAIN (LDD) REGIONS OF FINFET DEVICES - The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The mechanisms overcome the limitation by shadowing effects of ion implantation for advanced finFET devices. The highly doped source and drain regions are formed by epitaxial growing one or more doped silicon-containing materials from recesses formed in the fins. The dopants are then driven into the LDD regions by advanced annealing process, which can achieve targeted dopant levels and profiles in the LDD regions. | 09-18-2014 |
20150028355 | Method of Forming A Semiconductor Device - A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film. | 01-29-2015 |
20150072487 | Semiconductor Device and Method of Forming the Same - A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film. | 03-12-2015 |
Patent application number | Description | Published |
20090179875 | Flat display and driving method thereof - A flat display includes a substrate, multiple data lines, multiple scan lines, a source driving unit and a gate driving unit. The substrate includes a pixel array. The data lines are electrically connected to the pixel array. The scan lines including p groups of scan lines are electrically connected to the pixel array, wherein p is a positive integer. Some of the scan lines in the same group are not adjacent to each other. The source driving unit is electrically connected to the data lines. The gate driving unit includes p shift register circuits respectively enabling the p groups of scan lines. In a first frame period, p groups of scan lines are enabled according to a first sequence of groups, and in a second frame period, p groups of scan lines are enabled according to a second sequence of groups which is different from the first sequence of groups. | 07-16-2009 |
20090278776 | METHOD FOR DRIVING AN LCD DEVICE - A method for driving an LCD device having a plurality of sets of gate lines is disclosed. The method includes sequentially enabling odd gate lines of a first set of gate lines in ascending order for writing first-polarity data into corresponding pixels based on a first common voltage during a first interval, sequentially enabling even gate lines of the first set of gate lines in ascending order for writing second-polarity data into corresponding pixels based on a second common voltage during a second interval, sequentially enabling even gate lines of a second set of gate lines in descending order for writing second-polarity data into corresponding pixels based on the second common voltage during a third interval, and sequentially enabling odd gate lines of the second set of gate lines in descending order for writing first-polarity data into corresponding pixels based on the first common voltage during a fourth interval. | 11-12-2009 |
20100225570 | LIQUID CRYSTAL DEVICE WITH MULTI-DOT INVERSION - An LCD device includes a plurality of data lines, a plurality gate lines, a pixel matrix, and a source driver. The pixel matrix includes an mth pixel column and an (m+1)th pixel column. The odd-numbered pixels of the mth pixel column are coupled to an mth data line and corresponding odd-numbered gate lines. The even-numbered pixels of the mth pixel column is coupled to an (m+1)th data line and corresponding even-numbered gate lines. The odd-numbered pixels of the (m+1)th pixel column is coupled to the (m+1)th data line and corresponding odd-numbered gate lines. The even-numbered pixels of the (m+1)th pixel column is coupled to an (m+2)th data line and corresponding even-numbered gate lines. The gate driver outputs the data driving signals having a first polarity to the odd-numbered data lines, and outputs the data driving signals having a second polarity to the even-numbered data lines. | 09-09-2010 |
20100295764 | DISPLAY DEVICE - A display device includes a substrate, gate lines, data lines, data signal links, and contact vias. The substrate includes a display region, and a peripheral region surrounding the display region. The gate lines, data lines, data signal links, and contact vias are disposed within the display region of the substrate. The gate lines cross the data lines. Each of the data signal links is disposed between adjacent gate lines. Each of the contact vias is disposed between each of the data signal links and a corresponding data line, such that each of the data signal links is electrically connected with the corresponding data line. | 11-25-2010 |
20100315317 | DISPLAY DEVICE - A display device includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of first signal internal links. The first signal lines and the second signal lines are crossed and disposed in a display region of the substrate. The first signal internal links are disposed in the display region of the substrate, wherein each of the first signal internal links is electrically connected to a corresponding first signal line and disposed between two adjacent second signal lines. Each of the first signal internal links intersects the first signal lines, and the number of intersection points of each of the first signal internal links and the first signal lines is the same. | 12-16-2010 |
20120146981 | DRIVING METHOD OF DISPLAY APPARATUS AND DISPLAY APPARATUS FOR DISPLAYING FRAME - A driving method for a display apparatus. The display apparatus includes a plurality of first pixel units, a plurality of second pixel units, a first group of transmission lines and a second group of transmission lines. The first group of transmission lines and the second group of transmission lines are electronically connected to the plurality of first pixel units and the plurality of second pixel units, respectively. The driving method includes: generating a first and a second input signals including a plurality of input signals each having an identical waveform; and transmitting the first and the second input signals into the first group and second group of transmission lines such that the first and second input signals are transmitted to the plurality of first pixel units and the plurality of second pixel units in a plurality of different transmission directions, respectively. | 06-14-2012 |
20120313904 | DISPLAY APPARATUS AND DISPLAY DRIVING METHOD THEREOF - A display apparatus capable of enhancing pixel charging rate includes a substrate, a first column transmission line for transmitting a first column driving signal, a second column transmission line for transmitting a second column driving signal, and a row transmission line for transmitting a row driving signal. The substrate has plural row wiring areas and plural column wiring areas. The row and column wiring areas, substantially perpendicular to each other, are isolated by an insulation layer. The first and second column transmission lines, electrically isolated from each other, are disposed in one and the same column wiring area. The row transmission line is disposed in a corresponding row wiring area. | 12-13-2012 |
20140111406 | ELECTROLUMINESCENT DISPLAY PANEL AND DRIVING METHOD THEREOF - An electroluminescent display panel includes a plurality of sub-pixels; a plurality of scan lines, each of the scan lines being electrically connected to a first row of sub-pixels and a second row of sub-pixels of two adjacent rows; a plurality of first data lines electrically connected to the first rows of sub-pixels of corresponding columns respectively; a plurality of second data lines electrically connected to the second rows of sub-pixels of corresponding columns respectively; a scan driving unit for outputting a plurality of scanning signals; and a data driving unit for outputting a plurality of dada signals; wherein the scanning signals sequentially turn on two adjacent rows of sub-pixels via the scan lines, the data signals on the first data lines charge the first rows of sub-pixels of the corresponding columns, and the data signals on the second data lines charge the second rows of sub-pixels of the corresponding columns. | 04-24-2014 |
20140204069 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND DRIVING METHOD THEREOF - An organic light emitting diode (OLED) display device includes a plurality of OLED pixels, a gate driver, a source driver, and a voltage controller. Each of the OLED pixels includes a current control switch and an OLED. A first end of the current control switch is coupled to a first voltage source. A first end of the OLED is coupled to a second end of the current control switch, and a second end of the OLED is coupled to a second voltage source. The gate driver is configured to output scan signals to sequentially turn on the plurality of OLED pixels. The source driver is configured to output display voltages to the plurality of OLED pixels. The voltage controller is configured to adjust a voltage difference between the first voltage source and the second voltage source according to a maximum grey level value of display data of a frame. | 07-24-2014 |
20140340350 | SENSING CIRCUIT FOR TOUCH PANEL AND APPLIED TOUCH MODULE, ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF - A control method for a touch panel is provided. The control method includes: generating the first sensing signal; simultaneously delivering the first sensing signal to the first sensing electrodes in every idle scan period and receiving a plurality of second sensing signals from the second sensing electrodes; and determining whether the touch panel is being touched or not according to the received second sensing signal and switching the touch panel from the idle mode to the normal mode if the touch panel is being touched. Sensing circuit and touch panel are also provided. | 11-20-2014 |
Patent application number | Description | Published |
20100102294 | ORGANIC LIGHT EMITTING DIODE WITH NANO-DOTS AND FABRICATION METHOD THEREOF - An organic light emitting diode (OLED) with nano-dots and a fabrication method thereof are disclosed. The OLED apparatus comprises a substrate, a first electrically conductive layer, a first emission-auxiliary layer, an emissive layer, a second emission-auxiliary layer and a second electrically conductive layer. Its fabrication method is described below. Nano-dots with functional groups on the surface are incorporated into the emissive layer, the first emission-auxiliary layer or the second emission-auxiliary layer to form a layered electro-luminescent structure. By using the fabrication method, the resultant efficiency of the OLEDs can be markedly enhanced. | 04-29-2010 |
20100224832 | Modified nano-dot, fabrication method thereof and composition element thereof - The present invention discloses a modified nano-dot and a fabrication method thereof. The modified nano-dot comprises a surface portion having a functional group and a core portion comprising a polymeric metal oxide, polymeric metalloid oxide or polymeric metal alloy oxide. The mean particle size of the modified nano-dot is 1-100 nm, preferably 1-10 nm. The modified nano-dot capable of modulating a carrier flux can be further applied to the element manufacture in the organic semiconductor industry, optoelectronics industry, and solar cell industry. | 09-09-2010 |
20110031875 | High-molecule-based organic light-emitting diode and fabrication method thereof - The present invention discloses a high-molecule-based organic light-emitting diode (OLED) and a fabrication method thereof. The high-molecule-based OLED comprises a layer selected from a group consisting of an organic emissive layer, a first emission-auxiliary layer and a second emission-auxiliary layer. The organic emissive layer, first emission-auxiliary layer or second emission-auxiliary layer comprises a molecular material having a molecular weight of larger than approximately 730 g mol | 02-10-2011 |
20110168989 | High-molecule-based organic light-emitting diode and fabrication method thereof - The present invention discloses a high-molecule-based organic light-emitting diode (OLED) and a fabrication method thereof. The high-molecule-based OLED comprises a layer selected from a group consisting of an organic emissive layer, a first emission-auxiliary layer and a second emission-auxiliary layer. The organic emissive layer, first emission-auxiliary layer or second emission-auxiliary layer comprises a molecular material having a molecular weight of larger than approximately 730 g mol | 07-14-2011 |
20120061616 | MODIFIED NANO-DOT, FABRICATION METHOD THEREOF AND COMPOSITION ELEMENT THEREOF - The present invention discloses a modified nano-dot and a fabrication method thereof. The modified nano-dot comprises a surface portion having a functional group and a core portion comprising a polymeric metal oxide, polymeric metalloid oxide or polymeric metal alloy oxide. The mean particle size of the modified nano-dot is 1-100 nm, preferably 1-10 nm. The modified nano-dot capable of modulating a carrier flux can be further applied to the element manufacture in the organic semiconductor industry, optoelectronics industry, and solar cell industry. | 03-15-2012 |
Patent application number | Description | Published |
20100265180 | MOUSE WHEEL ASSEMBLY - A mouse wheel assembly is provided according to the present invention. The mouse wheel assembly includes a member and an optical module. The member has a pattern formed thereon. The optical module is adapted to illuminate the pattern on the member, capture an image of the pattern as a result of the illumination and recognize a feature change of the image of the pattern to obtain the change direction and change speed of the member. | 10-21-2010 |
20110127620 | MEMS INTEGRATED CHIP AND METHOD FOR MAKING SAME - The present invention discloses a MEMS (Micro-Electro-Mechanical System) chip and a method for making the MEMS chip. The MEMS chip comprises: a first substrate having a first surface and a second surface opposing each other; a microelectronic device area on the first surface; a first MEMS device area on the second surface; and a conductive interconnection structure electrically connecting the microelectronic device area and the first MEMS device area. | 06-02-2011 |
20120268375 | MOUSE WHEEL ASSEMBLY - A mouse wheel assembly is provided according to the present invention. The mouse wheel assembly includes a member and an optical module. The member has a pattern formed thereon. The optical module is adapted to illuminate the pattern on the member, capture an image of the pattern as a result of the illumination and recognize a feature change of the image of the pattern to obtain the change direction and change speed of the member. | 10-25-2012 |
20140076050 | OPTICAL ACCELEROMETER - There is provided an optical accelerometer including a first substrate, a second substrate, a spacer and a processing unit. The first substrate includes a frame, a movable member and at least one elastic member. Periodic slots are formed on the movable member along at least one direction to be served as a diffraction grating. The elastic member is connected between the frame and the movable member. The second substrate includes at least one sensing unit configured to detect a diffraction pattern formed by the diffraction grating. The spacer is disposed between the first substrate and the second substrate to define a predetermined height. The processing unit is coupled to the sensing unit and configured to calculate a 3D acceleration according to the diffraction pattern. | 03-20-2014 |
Patent application number | Description | Published |
20090230439 | Strain Bars in Stressed Layers of MOS Devices - A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region. | 09-17-2009 |
20100065913 | Performance-Aware Logic Operations for Generating Masks - A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks. | 03-18-2010 |
20110195554 | Strain Bars in Stressed Layers of MOS Devices - A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region. | 08-11-2011 |
20120043618 | Performance-Aware Logic Operations for Generating Masks - Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules. | 02-23-2012 |