| Patent application number | Description | Published |
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| 20090070642 | SYSTEM AND METHOD OF DYNAMICALLY MAPPING OUT FAULTY MEMORY AREAS - An information handling system is disclosed and can include a processor and a memory coupled to the processor. Further, the system can include a system reserved area that is accessible to the processor. The system reserved area can include a physical memory fault table having a plurality of bits and each bit in the physical memory fault table can represent an equal block of the memory. | 03-12-2009 |
| 20090077365 | System and method for analyzing CPU performance from a serial link front side bus - Monitoring of boot progress for a multiprocessor information handling system is performed with a test module running on a CPLD. RAM integrated in the CPLD stores boot progress information passed through an I/O buffer located between the processors and the firmware that boots the processors. Downloading of the boot progress from the RAM to an external device, such as through a serial port, provides a processor trace that is analysis and debugging of the firmware by recording processor operations through the boot progress. | 03-19-2009 |
| 20090193204 | SYSTEM AND METHOD OF ACCESSING MEMORY WITHIN AN INFORMATION HANDLING SYSTEM - A system and method of accessing memory within an information handling system are disclosed. In one form, a method of accessing memory can include detecting a first operating value of a first memory access node accessible to a first processor, and initiating operation of the first memory access node to a first data rate value. The method can also include initiating operation of a second memory access node to a second data rate value. In one form, the second data rate value can be different from the first data rate value. The method can also include enabling a first application access to either the first memory access node or the second memory access node via an operating system enabled by the processor. | 07-30-2009 |
| 20100023737 | TEST MODE INITIALIZATION - A test mode initialization system includes beginning a power-on self-test (POST) wherein the POST may be performed by determining whether a system under test is in a quick test mode, and in response to being in the quick test mode, initialize only a portion of all memory in the system under test and initialize only a portion of a plurality of central processor unit (CPU) cores. | 01-28-2010 |
| 20100192029 | Systems and Methods for Logging Correctable Memory Errors - In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM. | 07-29-2010 |
| 20100250876 | System and Method for Memory Architecture Configuration - Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory. | 09-30-2010 |
| 20120117302 | System and Method for Providing Instant Video in an Information Handling System - Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device. | 05-10-2012 |
| 20120159238 | System and Method for Recovering from a Configuration Error - A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system. | 06-21-2012 |
| 20140304546 | SYSTEM AND METHOD FOR RECOVERING FROM A CONFIGURATION ERROR - A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system. | 10-09-2014 |
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| 20080272837 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 11-06-2008 |
| 20080297217 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 12-04-2008 |
| 20100102858 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 04-29-2010 |
| 20100102876 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 04-29-2010 |
| 20100102877 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 04-29-2010 |
| 20120056767 | SIGNAL PROCESSING APPARATUS WITH SIGMA-DELTA MODULATING BLOCK COLLABORATING WITH NOTCH FILTERING BLOCK AND RELATED SIGNAL PROCESSING METHOD THEREOF - One signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is arranged to perform a notch filtering operation upon the signal output for generating a filtered signal output. Another signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is enabled for performing a notch filtering operation upon the signal output when the signal processing apparatus operates in a first operational mode, and the notch filtering block is disabled when the signal processing apparatus operates in a second operational mode. | 03-08-2012 |
| 20120074993 | INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD THEREFOR - An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component. | 03-29-2012 |
| 20120319883 | TIME-TO-DIGITAL CONVERTER - Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time. | 12-20-2012 |
| 20130112472 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 05-09-2013 |
| 20130118795 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 05-16-2013 |
| 20160056784 | LOW NOISE, PROGRAMMABLE GAIN CURRENT BUFFER - A receiver includes LNA-mixer arrangement, a current buffer arrangement and an analog filter arrangement. The LNA-mixer arrangement receives a plurality of input signals and provides a wide-band input match for a specified frequency range of operation. The LNA-mixer arrangement includes a plurality of LNA structures and a plurality of mixer structures where each of the LNA structure path is coupled to a single mixer structure. The LNA-mixer arrangement outputs a first signal. The current buffer arrangement receives the first signal and reduces the Image Rejection (IR) asymmetry between the high frequency portion and the low frequency portion of the first signal as well as provides a gain to the first signal. The current buffer arrangement outputs a second signal. The analog filter arrangement receives the second signals and perform filtering and calibration. | 02-25-2016 |
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| 20080320534 | Method for creating a subscriber cable channel and set-top box for use therewith - Media content is received from at least one external device that is coupled to a set-top box. Subscriber channel content is generated based on the media content. The subscriber channel content is transferred to a cable network to produce a subscriber cable channel. | 12-25-2008 |
| 20080320543 | Digital rights management for multiple devices with and methods for use therewith - Media content is received for a plurality of devices based on a user selection. The media content includes digital rights for the plurality of devices. The media content is transferred to at least one of the plurality of devices in accordance with the digital rights. | 12-25-2008 |
| 20080320596 | Distributed digital rights management system and methods for use therewith - A digital rights management (DRM) node module for use in a node of a public data includes a node data module that stores DRM data associated with a plurality of digital files, the DRM data including a plurality of DRM identifiers. A packet monitoring module receives the plurality of DRM identifiers from the node data module, that receives packets containing incoming content and compares the incoming content to the DRM identifier, and generates event data when the incoming content matches at least one of the DRM identifiers. A node reporting module receives the event data, and generates node report data based on the event data. | 12-25-2008 |
| 20090063314 | DISTRIBUTED DIGITAL RIGHTS MANAGEMENT NODE MODULE AND METHODS FOR USE THEREWITH - A digital rights management (DRM) node module for use in a node of a public data includes a node data module that stores DRM data associated with a plurality of digital files, the DRM data including a plurality of DRM identifiers. A packet monitoring module receives the plurality of DRM identifiers from the node data module, that receives packets containing incoming content and compares the incoming content to the DRM identifier, and generates event data when the incoming content matches at least one of the DRM identifiers. A node reporting module receives the event data, and generates node report data based on the event data. | 03-05-2009 |
| 20090163273 | HANDHELD VIDEO PLAYER AND OPTICAL STORAGE DISC FOR USE THEREWITH - An optical storage disc can be used in a handheld video player that includes a processing module, an interface module for receiving a video signal, and a display device. The optical storage disc includes a first portion that stores conditional access data and a second portion that stores a plurality of operational instructions including a video player application. When the optical storage disc is loaded in the handheld video player and when the plurality of operational instructions are executed by the processing module, the video player application descrambles the video signal received from the interface module using the conditional access data and displays video content from the video signal on the display device. | 06-25-2009 |
| 20090163281 | HANDHELD VIDEO PLAYER AND OPTICAL STORAGE DISC WITH ADVERTISING DATA FOR USE THEREWITH - An optical storage disc can be used in a handheld video player that includes a processing module, a interface module for receiving a video signal, and a display device. The optical storage disc includes a first portion that stores a plurality of advertising data; and a second portion that stores a plurality of operational instructions including a video player application. When the optical storage disc is loaded in the portable game console and when the plurality of operational instructions are executed by the processing module, the video player application decodes the video signal to produce a decoded video signal that includes at least one advertisement from the plurality of advertising data and displays video content from the video signal on the display device. | 06-25-2009 |
| 20110078721 | DIGITAL RIGHTS MANAGEMENT FOR MULTIPLE DEVICES AND METHODS FOR USE THEREWITH - Media content is received for a plurality of devices based on a user selection. The media content includes digital rights for the plurality of devices. The media content is transferred to at least one of the plurality of devices in accordance with the digital rights. | 03-31-2011 |
| 20110288971 | DISTRIBUTED DIGITAL RIGHTS MANAGEMENT NODE MODULE AND METHODS FOR USE THEREWITH - A digital rights management (DRM) node module for use in a node of a public data includes a node data module that stores DRM data associated with a plurality of digital files, the DRM data including a plurality of DRM identifiers. A packet monitoring module receives the plurality of DRM identifiers from the node data module, that receives packets containing incoming content and compares the incoming content to the DRM identifier, and generates event data when the incoming content matches at least one of the DRM identifiers. A node reporting module receives the event data, and generates node report data based on the event data. | 11-24-2011 |
| 20120062471 | HANDHELD DEVICE WITH GESTURE-BASED VIDEO INTERACTION AND METHODS FOR USE THEREWITH - A handheld device includes a wireless interface module that communicates a plurality of display interface data with a remote display device. The handheld device recognizes gestures in response to user interaction with the touch screen. A video application controls the communication of media signals between the handheld device and the remote display device via the display interface data, based on the recognized gestures. | 03-15-2012 |
| 20120066716 | METHOD FOR CREATING A PERSONALIZED SUBSCRIBER CHANNEL AND VIDEO PROCESSING DEVICE FOR USE THEREWITH - Media content is received from at least one external device that is coupled to a video processing device. Subscriber channel content is generated based on the media content. The subscriber channel content is transferred to a video distribution network to produce a personalized subscriber channel. | 03-15-2012 |
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| 20100187906 | System and Method for Optimizing Regulated Voltage Output Point - A device includes a plurality of voltage regulators, and a test module. Each of the voltage regulators are configured to provide a regulated voltage to one of a plurality of subsystems. The test module is in communication with the voltage regulators, and is configured to perform a subsystem component inventory for each of the subsystems at a start of a power-on self-test of the device, to determine a configuration of the device. The test module is also configured to capture first voltage data for the subsystems during an idle operation, to capture second voltage data for the subsystems during a stressed operation, and to set a voltage set point for each of the regulated voltages provided by one of the voltage regulators based on the subsystem component inventory, a power requirement table, or the first and second voltage data. | 07-29-2010 |
| 20100191991 | System and Method for Using an On-DIMM Remote Sense for Performance and Power Optimization - A system includes a dual in-line memory module and a system board. The dual in-line memory module includes a plurality of dynamic random access memory devices, and a system management interface. The system management interface is configured to measure a first voltage provided to the dynamic random access memory devices, and configured to digitize the first voltage. The system board includes a test module and a voltage regulator. The test module is configured to receive the digitized first voltage via a connector pin between the dual in-line memory module and the system board, and configured to compare the first voltage to a first threshold voltage. The voltage regulator is configured to adjust a remote sense target voltage for the system management interface when the first voltage is less than the first threshold voltage. | 07-29-2010 |
| 20130194726 | RACK-LEVEL SCALABLE AND MODULAR POWER INFRASTRUCTURE - In accordance with the present disclosure, a scalable and modular rack-level power infrastructure is described. The power infrastructure may include a power distribution unit (PDU), which receives alternating current (AC) power from an external power source. The PDU may be coupled to a busbar and output DC power to the busbar. The busbar may be coupled to a server within a rack-server system and provide DC power to the server. Additionally, the infrastructure may include a battery back-up unit (BBU) element coupled to the busbar. The BBU element may charge from and discharge to the busbar. | 08-01-2013 |
| 20130198532 | SYSTEMS AND METHODS FOR COUPLING AC POWER TO A RACK-LEVEL POWER INFRASTRUCTURE - In accordance with the present disclosure, a detachable power cable interface box (PCIB) for coupling AC power to a rack-level power infrastructure is described. The detachable PCIB includes a body section and a terminal disposed within the body section. The terminal may be coupled to an AC power source. A wiring block may also be disposed within the body, and the modular wiring block may be coupled to the terminal. The wiring block may arrange power input from the AC power source into a pre-determined output configuration corresponding to a detachable interface. The system may also include the detachable interface, and the detachable interface may be configured to couple with an integrated connector of the rack-level power infrastructure. The detachable interface may be common to all types of AC power sources. | 08-01-2013 |
| 20130198533 | SYSTEMS AND METHODS FOR PROVIDING SCALABLE UNINTERRUPTABLE DC POWER TO A RACK-LEVEL POWER INFRASTRUCTURE - In accordance with the present disclosure, a battery back-up unit (BBU) element for providing uninterruptable direct current (DC) power in a rack-level power infrastructure is describe. The BBU element may include a rack-mountable chassis with a battery drawer. A battery may be disposed within the battery drawer, and at least one power module may be coupled to the battery. The BBU element may also include a power module controller that causes the battery to charge from or discharge to a busbar coupled to the BBU element. The power module controller may also communicate power management information to a power infrastructure controller. | 08-01-2013 |
| 20140192456 | SYSTEMS AND METHODS FOR COUPLING AC POWER TO A RACK-LEVEL POWER INFRASTRUCTURE - In accordance with the present disclosure, a detachable power cable interface box (PCIB) for coupling AC power to a rack-level power infrastructure is described. The detachable PCIB includes a body section and a terminal disposed within the body section. The terminal may be coupled to an AC power source. A wiring block may also be disposed within the body, and the modular wiring block may be coupled to the terminal. The wiring block may arrange power input from the AC power source into a pre-determined output configuration corresponding to a detachable interface. The system may also include the detachable interface, and the detachable interface may be configured to couple with an integrated connector of the rack-level power infrastructure. The detachable interface may be common to all types of AC power sources. | 07-10-2014 |
| 20150177806 | METHOD TO SELECTIVELY ACTIVATE POWER OUTLETS IN A FLEXIBLE AND SCALABLE POWER AND SYSTEM MANAGEMENT INFRASTRUCTURE FOR A DATA MANAGEMENT SYSTEM - A power switching system, a method, and an information handling system (IHS) enables selective activation and de-activation of respective alternating current (AC) outlets of a plurality of AC outlets within an AC switch (ACS). The AC switch includes a decoder circuit that is couple via a control interface to a management controller (MC) and receives control commands from the control interface. In response to receipt of the control command, the decoder circuit decodes the command in order to provide control signals to one or more of a number of serial voltage relays, which are each respectively coupled to the AC outlets. The AC switch utilizes the decoder circuit to respectively configure the serial voltage relays using the control signals. By configuring the serial voltage relays, the MC provides and/or removes respective connections between AC inputs and AC outlets, which selectively activates and/or de-activates respective AC outlets. | 06-25-2015 |
| 20150177814 | PREDICTIVE POWER CAPPING AND POWER ALLOCATION TO COMPUTING NODES IN A RACK-BASED INFORMATION HANDLING SYSTEM - A computer-implemented method enables rack-level predictive power capping and power budget allocation to processing nodes in a rack-based IHS. A rack-level management controller receives node-level power-usage data and settings from several block controllers, including current power consumption and an initial power budget for each node. A power consumption profile is generated based on the power-usage data for each node. A total available system power of the IHS is identified. A system power cap is determined based on the power consumption profiles and the total available system power. A current power budget is determined for each node based on an analysis of at least one of the power consumption profile, the initial power budget, the current power consumption, the system power cap, and the total available system power. A power subsystem regulates power budgeted and supplied to each node based on the power consumption profiles and the system power cap. | 06-25-2015 |
| 20150180234 | RACK POWER DISTRIBUTION VIA MODULAR, EXPANDABLE BUS BAR FOR MODULAR AND SCALABLE/EXPANDABLE INFORMATION HANDLING SYSTEM - A rack-based information handling system (IHS) includes a rack having a modular structure that supports insertion from a front of the rack of different numbers and sizes of information technology (IT) gear to create one or more IT nodes. Power bay chassis is received in the rack with a power distribution unit directed towards a rear of the rack. A modular busbar assembly is attached to the rear of the rack. A first vertical busbar segment is in direct electrical connection with the power distribution unit and spans one or more nodes to provide hot pluggable electrical power to an aft-directed connection of an IT node inserted into the rack. A second busbar segment can be attached to the first vertical busbar to electrically communicate with the power distribution unit and span an additional node adjacent to the one or more nodes to provide electrical power to the adjacent node. | 06-25-2015 |
| 20150189787 | MODULAR, SCALABLE, EXPANDABLE, RACK-BASED INFORMATION HANDLING SYSTEM - A modular, scalable and expandable (MSE) rack-based information handling system (RIHS) includes: a rack assembly having a frame that defines: a front bay chassis with height, depth and width dimensions that enable insertion of a plurality of different sizes of IT gear; and a rear bay that accommodates power and cooling components to support operation of the different sizes of IT gear. The power and cooling for the IT gear are provided from the rear bay and are separate from and independent of the IT gear installed within the front bay chassis. The rack assembly further includes a power and management chassis in which is inserted a power and management module having power and management components located thereon to provide rack-level power and management. A modular configuration of fan modules are inserted within fan receptacles within the rear bay to provide block level cooling of adjacent blocks of IT gear. | 07-02-2015 |
| 20150357865 | SYSTEMS AND METHODS FOR PROVIDING SCALABLE UNINTERRUPTABLE DC POWER TO A RACK-LEVEL POWER INFRASTRUCTURE - In accordance with the present disclosure, a battery back-up unit (BBU) element for providing uninterruptable direct current (DC) power in a rack-level power infrastructure is describe. The BBU element may include a rack-mountable chassis with a battery drawer. A battery may be disposed within the battery drawer, and at least one power module may be coupled to the battery. The BBU element may also include a power module controller that causes the battery to charge from or discharge to a busbar coupled to the BBU element. The power module controller may also communicate power management information to a power infrastructure controller. | 12-10-2015 |
| 20150372462 | SYSTEMS AND METHODS FOR COUPLING AC POWER TO A RACK-LEVEL POWER INFRASTRUCTURE - In accordance with the present disclosure, a detachable power cable interface box (PCIB) for coupling AC power to a rack-level power infrastructure is described. The detachable PCIB includes a body section and a terminal disposed within the body section. The terminal may be coupled to an AC power source. A wiring block may also be disposed within the body, and the modular wiring block may be coupled to the terminal. The wiring block may arrange power input from the AC power source into a pre-determined output configuration corresponding to a detachable interface. The system may also include the detachable interface, and the detachable interface may be configured to couple with an integrated connector of the rack-level power infrastructure. The detachable interface may be common to all types of AC power sources. | 12-24-2015 |
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| 20100312812 | Decimal Floating-Point Adder with Leading Zero Anticipation - A decimal floating-point (DFP) adder includes a decimal leading-zero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a leading zero count for the significand. The DFP adder adds or subtracts the DFP operands to obtain a DFP result. The LZA determines the leading zero count associated with the significand of the DFP result. The LZA operates at least partially in parallel with circuitry (in the DFP adder) that computes the DFP result. The LZA does not wait for that circuitry to finish computation of the DFP result. Instead it “anticipates” the number of leading zeros that the result's significand will contain. | 12-09-2010 |
| 20130282779 | DECIMAL FLOATING-POINT ADDER WITH LEADING ZERO ANTICIPATION - A decimal floating-point (DFP) adder includes a decimal leading-zero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a leading zero count for the significand. The DFP adder adds or subtracts the DFP operands to obtain a DFP result. The LZA determines the leading zero count associated with the significand of the DFP result. The LZA operates at least partially in parallel with circuitry (in the DFP adder) that computes the DFP result. The LZA does not wait for that circuitry to finish computation of the DFP result. Instead it “anticipates” the number of leading zeros that the result's significand will contain. | 10-24-2013 |
| 20140067895 | MICROARCHITECTURE FOR FLOATING POINT FUSED MULTIPLY-ADD WITH EXPONENT SCALING - Systems and methods for implementing a floating point fused multiply and accumulate with scaling (FMASc) operation. A floating point unit receives input multiplier, multiplicand, addend, and scaling factor operands. A multiplier block is configured to multiply mantissas of the multiplier and multiplicand to generate an intermediate product. Alignment logic is configured to pre-align the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand, and accumulation logic is configured to add or subtract a mantissa of the pre-aligned addend with the intermediate product to obtain a result of the floating point unit. Normalization and rounding are performed on the result, avoiding rounding during intermediate stages. | 03-06-2014 |
| 20150347089 | MICROARCHITECTURE FOR FLOATING POINT FUSED MULTIPLY-ADD WITH EXPONENT SCALING - Systems and methods for implementing a floating point fused multiply and accumulate with scaling (FMASc) operation. A floating point unit receives input multiplier, multiplicand, addend, and scaling factor operands. A multiplier block is configured to multiply mantissas of the multiplier and multiplicand to generate an intermediate product. Alignment logic is configured to pre-align the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand, and accumulation logic is configured to add or subtract a mantissa of the pre-aligned addend with the intermediate product to obtain a result of the floating point unit. Normalization and rounding are performed on the result, avoiding rounding during intermediate stages. | 12-03-2015 |
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| 20160056979 | DUTY-CYCLED EQUALIZATIONS - An information handling system (IHS) selectively performs duty-cycled equalization of data transmission on a communication link between a sending component and a receiving component. A controller activates an equalizer associated with the communication link. Following equalizer convergence, the controller determines power consumption and/or data throughput corresponding to data samples propagated over the communication link. If power consumption and/or data throughput do not exceed respective specified threshold values, the controller maintains or applies continuous equalization. However, if power consumption and/or data throughput exceed the respective threshold values, the controller initiates duty-cycled equalization using a selected duty cycle value. The duty-cycled equalization activates the equalizer during the first interval to minimize accumulating inter-symbol interference (ISI) effects associated with a first set of data samples, and de-activates the equalizer during a second interval enabling a second set of data samples to bypass equalization, while satisfying power consumption and signal quality requirements. | 02-25-2016 |
| 20160105296 | Power Aware Receiver/Transmitter Adaptation for High Speed Serial Interfaces - A receiver includes first and second equalization modules adapted to provide first and second compensations to a data signal, and a control module including a list that identifies the first equalization module as being less efficient than the second. The control module provides first and second compensation levels of the first and second compensations, such that the first and second compensations operate on the data signal to meet a bit error rate (BER) target, lowers the first compensation to reduce the power consumption of the receiver based on the list, and determines whether, in response to an increase in the level of the second compensation the BER target is met. | 04-14-2016 |
| 20160134443 | Repeatable Backchannel Link Adaptation for High Speed Serial Interfaces - A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values. | 05-12-2016 |
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| 20140054549 | GATED CIRCUIT STRUCTURE WITH ULTRA-THIN, EPITAXIALLY-GROWN TUNNEL AND CHANNEL LAYER - A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer. | 02-27-2014 |
| 20150093884 | METHODS OF FORMING SEMICONDUCTOR PATTERNS INCLUDING REDUCED DISLOCATION DEFECTS AND DEVICES FORMED USING SUCH METHODS - Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate. | 04-02-2015 |
| 20150270120 | METHODS OF FORMING LOW-DEFECT STRAIN-RELAXED LAYERS ON LATTICE-MISMATCHED SUBSTRATES AND RELATED SEMICONDUCTOR STRUCTURES AND DEVICES - Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer that is lattice-matched with the semiconductor substrate is formed on the porous region. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer being a strained layer as formed. The second semiconductor layer is then relaxed. | 09-24-2015 |
| 20150318355 | METHODS OF FORMING DEFECT-FREE SRB ONTO LATTICE-MISMATCHED SUBSTRATES AND DEFECT-FREE FINS ON INSULATORS - A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures. | 11-05-2015 |
| 20160042956 | INTERFACE LAYER FOR GATE STACK USING 03 POST TREATMENT - Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment that mixes with and penetrates the first dielectric layer and reacts with the semiconductor body to form a new interface layer; and performing gate stack processing, including deposition of a gate electrode. | 02-11-2016 |
| 20160071729 | RECTANGULAR NANOSHEET FABRICATION - Exemplary embodiments provide methods for fabricating a nanosheet structure suitable for field-effect transistor (FET) fabrication. Aspects of exemplary embodiment include selecting an active material that will serve as a channel material in the nanosheet structure, a substrate suitable for epitaxial growth of the active material, and a sacrificial material to be used during fabrication of the nanosheet structure; growing a stack of alternating layers of active and sacrificial materials over the substrate; and selectively etching the sacrificial material, wherein due to the properties of the sacrificial material, the selective etch results in remaining layers of active material having an aspect ratio greater than 1 and substantially a same thickness and atomic smoothness along the entire cross-sectional width of each active material layer perpendicular to current flow. | 03-10-2016 |
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| 20090034352 | METHOD AND CIRCUIT FOR PREVENTING HIGH VOLTAGE MEMORY DISTURB - A circuit and method reduces disturb in a memory array resulting from one of two supply voltages dropping below a predetermined value. Memory control logic is operated using a logic power domain. Higher voltages than that of the logic power domain are generated in response to an oscillator oscillating. The higher voltages are used to operate the memory array. Operation of the oscillator is controlled with the memory control logic when the logic power domain is at least at a first level or value. The oscillator is disabled when the logic power domain is below the first level. The disabling of the oscillator has the effect of preventing generation of the higher voltages. This facilitates preventing the higher voltages from reaching the memory array when they may not be properly controlled. | 02-05-2009 |
| 20090059629 | VOLTAGE REGULATOR FOR INTEGRATED CIRCUITS - A voltage regulator for a charge pump includes a capacitor divider and a reset circuit. The capacitor divider produces, based on an input voltage (VPP), a sample voltage at a sampling node. The sampling node and a reference voltage VREF are connected to respective inputs of a comparator that generates an enable signal for the charge pump. The reset circuit connects to the divider and includes a first transistor connected between the sampling node and a biasing node. During a sampling mode, the reset circuit biases VDS of the first transistor to approximately zero at the regulation point to minimize subthreshold IDS. During reset intervals, the reset circuit applies VREF to the biasing node. The reset circuit may include a second transistor connected between the biasing node and a known level (e.g., ground) and a biasing transistor connected between the biasing node and VREF. | 03-05-2009 |
| 20120195124 | PROGRAMMING A NON-VOLATILE MEMORY - In a system having a plurality of non-volatile memory cells, a method includes performing hot carrier injection on a first non-volatile memory cell in a first mode of programming. In the first mode, current flows from a first current electrode to a second electrode of the first non-volatile memory cell and charge is transferred from the current to a floating gate of the first non-volatile memory cell at a location nearer the first current electrode than the second current electrode. The method further includes performing hot carrier injection on the first non-volatile memory cell in a second mode of programming. In the second mode, current flows from the second current electrode to the first electrode of the first non-volatile memory cell and charge is transferred from the current to the floating gate of the first non-volatile memory cell at a location nearer the second current electrode than the first current electrode. | 08-02-2012 |
| 20130107621 | BUILT-IN SELF TRIM FOR NON-VOLATILE MEMORY REFERENCE CURRENT | 05-02-2013 |
| 20130194874 | Dynamic Healing Of Non-Volatile Memory Cells - Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques. | 08-01-2013 |
| 20130194875 | STRUCTURE AND METHOD FOR HEALING TUNNEL DIELECTRIC OF NON-VOLATILE MEMORY CELLS - A semiconductor device comprises an array of memory cells. Each of the memory cells includes a tunnel dielectric, a well region including a first current electrode and a second current electrode, and a control gate. The first and second current electrodes are adjacent one side of the tunnel dielectric and the control gate is adjacent another side of the tunnel dielectric. A controller is coupled to the memory cells. The controller includes logic to determine when to perform a healing process in the tunnel dielectric of the memory cells, and to apply a first voltage to the first current electrode of the memory cells during the healing process to remove trapped electrons and holes from the tunnel dielectric. | 08-01-2013 |
| 20140029335 | METHODS AND SYSTEMS FOR ADJUSTING NVM CELL BIAS CONDITIONS BASED UPON OPERATING TEMPERATURE TO REDUCE PERFORMANCE DEGRADATION - Methods and systems are disclosed for making temperature-based adjustments to bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store temperature-based bias condition information in storage circuitry. The disclosed embodiments select and apply bias conditions for the NVM cells based upon temperature measurements. | 01-30-2014 |
| 20140029350 | METHODS AND SYSTEMS FOR ADJUSTING NVM CELL BIAS CONDITIONS FOR READ/VERIFY OPERATIONS TO COMPENSATE FOR PERFORMANCE DEGRADATION - Methods and systems are disclosed for adjusting read/verify bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having a NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and read/verify bias condition information within storage circuitry. The disclosed embodiments adjust read/verify bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations. | 01-30-2014 |
| 20140029351 | METHODS AND SYSTEMS FOR ADJUSTING NVM CELL BIAS CONDITIONS FOR PROGRAM/ERASE OPERATIONS TO REDUCE PERFORMANCE DEGRADATION - Methods and systems are disclosed for adjusting program/erase bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and program/erase bias condition information within storage circuitry. The disclosed embodiments adjust program/erase bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations and interim verify based performance degradation determinations. | 01-30-2014 |
| 20140063946 | NON-VOLATILE MEMORY (NVM) THAT USES SOFT PROGRAMMING - A semiconductor memory device comprises a memory controller, and an array of memory cells coupled to communicate with the memory controller. The memory controller is configured to perform a first soft program operation using first soft program voltages and a first soft program verify level, and determine whether a first charge trapping threshold has been reached. When the first charge trapping threshold has been reached, a second soft program operation is performed using second soft program voltages and a second soft program verify level. | 03-06-2014 |
| 20140160869 | BUILT-IN SELF TRIM FOR NON-VOLATILE MEMORY REFERENCE CURRENT - A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value. | 06-12-2014 |
| 20140269111 | NON-VOLATILE MEMORY (NVM) WITH BLOCK-SIZE-AWARE PROGRAM/ERASE - A memory includes a plurality of blocks in which each block includes a plurality of memory cells. The memory includes a set of charge pumps which apply voltages to the plurality of blocks. A method includes selecting a block of the plurality of memory blocks; determining an array size of the selected block; determining a set of program/erase voltages based on the array size and temperature from a temperature sensor; and programming/erasing the selected block, wherein the set of program/erase voltages are applied by the set of charge pumps during the programming/erasing of the selected block. | 09-18-2014 |
| 20140321211 | NON-VOLATILE MEMORY (NVM) WITH VARIABLE VERIFY OPERATIONS - A method of erasing a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array. Erase pulses of the first number are applied to the NVM array. A first verify of the NVM is performed for a first time after commencing the applying after the first number has been reached. | 10-30-2014 |
| 20140321212 | NON-VOLATILE MEMORY (NVM) WITH VARIABLE VERIFY OPERATIONS - A method of soft programming a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array and applying the first number of soft program pulses to a section of the NVM array. A first soft program verify of the section of the NVM array is then performed for a first time after completing the applying the first number of soft program pulses. | 10-30-2014 |
| 20150023106 | Adaptive Erase Recovery For Non-Volatile Memory (NVM) Systems - Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system. | 01-22-2015 |
| 20150049555 | Extended Protection For Embedded Erase Of Non-Volatile Memory Cells - Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (V | 02-19-2015 |
| 20150085593 | NON-VOLATILE MEMORY (NVM) WITH DYNAMICALLY ADJUSTED REFERENCE CURRENT - A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation. | 03-26-2015 |
| 20150117112 | ADAPTIVE ERASE METHODS FOR NON-VOLATILE MEMORY - A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks. | 04-30-2015 |
