Patent application number | Description | Published |
20080260739 | Use of Anti-Mortalin 2 Antibody and Functional Nucleic Acid for Cancer Therapies - The present invention relates to cancer therapies using an antibody that binds to mortalin 2 and a functional nucleic acid. Mortalin expression was found to be upregulated in immortalized cells and tumor tissues. Immortalized human cells highly expressing mortalin showed anchorage-independent growth. When the K antibody, which is a specific anti-mortalin antibody, was injected into a tumor of a nude mouse, tumor growth was suppressed or the tumor shrank compared with the case of a control. In accordance with the present invention, the use of a specific anti-mortalin antibody (K antibody) for tumor therapies and the use of such antibody as a carrier molecule for transportation of immunotoxicin and the like into cells are provided. It has been shown that mortalin can be a target for cancer therapies. In accordance with the present invention, a novel and effective anticancer agent is provided. In addition, an anti-mortalin antibody that is internalized by cells is developed. Thus, various applications using such antibody are provided. | 10-23-2008 |
20100112591 | Tumor Suppressor Gene - A full-length cDNA encoding novel proteins involved in the control of cell proliferation (human Gros1-L and S) was successfully isolated from the human testis cDNA libraries. A full-length cDNA encoding the mouse homologues of the human Gros1 (mouse Gros1-L and S) was also isolated. The colony forming activity of cells exogenously expressing Gros1-L was significantly reduced, while that of cells expressing Gros1 antisense RNA was significantly increased. | 05-06-2010 |
20110008913 | TUMOR SUPPRESSOR GENE - A full-length cDNA encoding novel proteins involved in the control of cell proliferation (human Gros1-L and S) was successfully isolated from the human testis cDNA libraries. A full-length cDNA encoding the mouse homologues of the human Gros1 (mouse Gros1-L and S) was also isolated. The colony forming activity of cells exogenously expressing Gros1-L was significantly reduced, while that of cells expressing Gros1 antisense RNA was significantly increased. | 01-13-2011 |
20120156722 | Tumor Suppressor Gene - A full-length cDNA encoding novel proteins involved in the control of cell proliferation (human Gros1-L and S) was successfully isolated from the human testis cDNA libraries. A full-length cDNA encoding the mouse homologues of the human Gros1 (mouse Gros1-L and S) was also isolated. The colony forming activity of cells exogenously expressing Gros1-L was significantly reduced, while that of cells expressing Gros1 antisense RNA was significantly increased. | 06-21-2012 |
Patent application number | Description | Published |
20100283517 | CHARGE PUMP FOR PHASE LOCKED LOOP - A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal ( | 11-11-2010 |
20110169553 | TEMPERATURE COMPENSATED CURRENT REFERENCE CIRCUIT - A temperature compensated current reference circuit has a differential amplifier and a first feedback transistor with a gate coupled to the differential amplifier output. The first feedback transistor couples a supply voltage line to an inverting input of the differential amplifier. There is also a second feedback transistor with a gate coupled to the differential amplifier output, which couples the supply voltage line to a non-inverting input of the differential amplifier. A first temperature dependent conductor couples the inverting input to ground. A primary reference resistor and a second temperature dependent conductor are connected in series and couple the non-inverting input to ground. An output current control transistor has a gate and one other electrode coupled together and a third electrode coupled to the supply voltage line. A secondary reference resistor and a conductivity change sensing transistor are connected in series and couple the gate of the output current control transistor to ground. The conductivity change sensing transistor has a gate coupled to the second one of the two differential inputs. There is a temperature compensation current reference output circuit that has a current reference transistor, an input coupled to the differential amplifier output and another input is coupled to the gate of the output current control transistor. | 07-14-2011 |
20110215849 | CHARGE PUMP FOR PHASE LOCKED LOOP - A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal ( | 09-08-2011 |
20120033772 | SYNCHRONISER CIRCUIT AND METHOD - A synchronizer circuit and method for transferring data between mutually asynchronous source and destination clock domains. An input synchronizer cell clocked at an input clock frequency receives input data from the source domain and produces a corresponding intermediate signal. A frequency divider produces a divided clock signal whose frequency is equal to the input clock frequency divided by an integer. An output synchronizer module comprises first and second cascaded synchronizer cells clocked at the divided clock frequency, receives the intermediate signal and produces a corresponding output signal for the destination clock domain. | 02-09-2012 |
20120176169 | DIGITAL PHASE LOCKED LOOP WITH REDUCED SWITCHING NOISE - A method to operate a digital phase locked loop (DPLL) in which the DPLL includes a phase-frequency detector that compares the frequency of a reference signal with a feedback signal to generate an error signal. The error signal is used to generate first and second control words. Binary current control word bits and thermometric current control word bits are generated using the first and second control words, respectively. A binary controller switches a first set of binary current sources prior to a frequency lock being achieved using the binary current control word bits and the thermometric current control word bits are held at a predetermined value. After achieving the frequency lock, the binary current sources are fixed and then a thermometric controller switches a second set of thermometric current sources using the thermometric current control word bits. Operating the DPLL using the binary controller before the frequency lock and the thermometric controller after the frequency lock reduces switching noise and achieves stable loop dynamics. | 07-12-2012 |
20120249198 | DUAL LOOP PHASE LOCKED LOOP WITH LOW VOLTAGE-CONTROLLED OSCILLATOR GAIN - A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply. | 10-04-2012 |
20120319788 | RELAXATION OSCILLATOR WITH LOW POWER CONSUMPTION - A relaxation oscillator for generating oscillator signal includes a ramp voltage generating circuit, a reference voltage generating circuit, a reference voltage switching circuit, and a digital logic circuit. The reference voltage generating circuit generates one or more reference voltages and the ramp voltage generating circuit generates one or more ramp voltages. The ramp voltages are compared with each of the reference voltages by sequentially switching the reference voltages using a reference voltage switching signal generated by the reference voltage switching circuit. The oscillator signal is generated by the digital logic circuit based on the results of the comparisons. | 12-20-2012 |
20140015509 | BANDGAP REFERENCE CIRCUIT AND REGULATOR CIRCUIT WITH COMMON AMPLIFIER - A bandgap voltage reference and voltage regulator system includes a bandgap voltage reference circuit and a voltage regulator circuit that share a single, common amplifier. The amplifier acts as a gain stage for the reference circuit and as an error amplifier for a driver stage of the regulator circuit. The regulator circuit has an input reference generated by the reference circuit, and the reference circuit acts as a load to the driver stage, obviating the need for a bias resistance network. By sharing the amplifier and obviating the need for a resistance network, the area and overall quiescent current of the system are reduced. The system can be implemented in CMOS/BiCMOS technology and is suited for low power applications. | 01-16-2014 |
20140118078 | RELAXATION OSCILLATOR - A relaxation oscillator for generating an output clock signal includes a RC circuit, a bias generation stage, first and second comparator stages, and a logic circuit. The RC circuit generates first and second comparator input signals that are transmitted to the first and second comparator stages. The bias generation stage generates first and second bias voltages that are provided to each of the first and second comparator stages. The first and second comparator stages generate first and second comparator output signals, respectively, based on the first and second comparator input signals and the first and second bias voltages. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal. | 05-01-2014 |
20140139201 | LOW-POWER VOLTAGE TAMPER DETECTION - Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage. | 05-22-2014 |
20140197806 | CAPACITOR CHARGING CIRCUIT WITH LOW SUB-THRESHOLD TRANSISTOR LEAKAGE CURRENT - A capacitor charging circuit has input, output and control nodes, first and second series connected primary FETs, and first and second leakage current reduction FETs. All of the FETs have their gates coupled to the control node. The first primary FET is coupled between the input and output nodes, and the second primary FET is coupled between the output node and a leakage current reduction node. The first leakage current reduction FET is coupled between a supply line and the leakage current reduction node, and the second leakage current reduction FET is coupled between the leakage current reduction node and ground. When a control signal at the control node is low, the first primary FET and the first leakage current reduction FET are conductive, and the second primary FET and the second leakage current reduction FET are non-conductive, which eliminates sub-threshold leakage current flowing through the second primary FET. | 07-17-2014 |
20140210564 | RELAXATION OSCILLATOR WITH SELF-BIASED COMPARATOR - A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal. | 07-31-2014 |
Patent application number | Description | Published |
20110291724 | DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier. | 12-01-2011 |
20120133405 | PLL START-UP CIRCUIT - A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal. | 05-31-2012 |
20160056811 | TESTABLE POWER-ON-RESET CIRCUIT - An integrated circuit with a testable power-on-reset (POR) circuit includes a voltage divider, an inverter, a level-shifter, a buffer and a flip-flop. The voltage divider receives a first supply voltage and generates a second supply voltage. The POR circuit receives the second supply voltage and generates a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold. The level-shifter receives the POR voltage signal and an inverted POR voltage signal from the inverter circuit and generates a level-shifted POR voltage signal at a voltage level of the first supply voltage. The buffer receives the level-shifted POR voltage signal and outputs a delayed level-shifted POR voltage signal. The flip-flop receives the first supply voltage as data input, the delayed level-shifted POR voltage signal as clock input, the level-shifted POR voltage signal as reset input, and outputs a voltage-monitor signal at the voltage level of the first supply voltage. | 02-25-2016 |
Patent application number | Description | Published |
20100022182 | SATTELLITE RADIO SYSTEM AND METHOD OF ACTIVATING SAME - A satellite radio system may include at least one computing device configured to receive a transaction date associated with a vehicle, to determine a preactivation duration based on the date, and to determine whether the preactivation duration exceeds a predetermined time period. The at least one computing device may be further configured to initiate the transmission of deactivation information for a satellite radio module in the vehicle if the preactivation duration exceeds the predetermined time period to disable the module from playing satellite broadcast signals. | 01-28-2010 |
20100240337 | System and Method for Automatic Storage and Retrieval of Emergency Information - A vehicle communication system may retrieve “in case of emergency” (ICE) information from a wireless device. The ICE information may include contact information, medical information, etc., and may be transferred to an emergency provider, if the vehicle communication system places an emergency call. The information may also be retrieved at some point before an emergency call is placed and stored in a memory circuit of the vehicle communication system. | 09-23-2010 |
20110225228 | METHOD AND SYSTEMS FOR QUEUING MESSAGES FOR VEHICLE-RELATED SERVICES - Various embodiments include a method and system for queuing messages for transmission to/from a vehicle. One or more messages from one or more applications for performing one or more vehicle-related events may be received. The one or more messages may include a message identifier for each of the one or more vehicle applications to correlate the one or more messages with the one or more applications. The messages may be queued for transmission. A vehicle's connectivity to a wireless network is determined and, if the vehicle is connected to the wireless network, the one or more queued messages are transmitted. The one or more vehicle-related events based on the one or more messages are performed. | 09-15-2011 |
20110295444 | METHODS AND SYSTEMS FOR IMPLEMENTING AND ENFORCING SECURITY AND RESOURCE POLICIES FOR A VEHICLE - In one or more embodiments, a vehicle resource usage control system includes a vehicle computer having security policies that define usage rules for one or more vehicle resources. One or more devices communicating with the vehicle computer may have installed in memory software applications that use one or more vehicle resources for operation. Programmed instructions may be received that define which of the one or more vehicle resources the software applications use for operation. These programmed instructions may be associated with the one or more security policies. The security policy associated with the software applications may be determined based on the programmed instructions. Operation of the software applications may be permitted according to the security policy. | 12-01-2011 |
20110296037 | METHODS AND SYSTEMS FOR INTERFACING WITH A VEHICLE COMPUTING SYSTEM OVER MULTIPLE DATA TRANSPORT CHANNELS - In one or more embodiments, two or more devices may interface with a computing system over multiple communication channels. A connection may be established between a computing system and two or more devices communicating data using different communication protocols. The communication protocol of the two or more devices may be determined and a general transport protocol for communicating data with the two or more devices based on the respective communication protocols may be imposed on the communication protocol of the two or more devices. Data may be communicated with the two or more devices based on the general transport protocol. An event may be performed at the vehicle computing system or the two or more devices based on the data. | 12-01-2011 |
20120030512 | PROVISIONING OF DATA TO A VEHICLE INFOTAINMENT COMPUTING SYSTEM - Various embodiments include a software provisioning system and method for a vehicle infotainment computer. Software provisioning of the vehicle infotainment computer may occur during vehicle assembly. A software provisioning request may be received for custom installing software to the vehicle infotainment computer. The custom install may be based on a customization schedule which may include a location identifier (such as uniform resource identifiers or file paths) for locating the software. In response to the request, the software may be located on a provisioning server or a portable memory device based on the customization schedule. The software may be transmitted to memory of the vehicle infotainment computer and custom installed on the vehicle infotainment computer. | 02-02-2012 |
20120039248 | METHOD AND SYSTEM FOR IN-VEHICLE WIRELESS CONNECTIVITY - One embodiment of the present invention is a vehicle computer system for establishing in-vehicle wireless connectivity to remote computer network, e.g., the Internet. The system may include a processor in communication with a human machine interface (HMI) for control by a user. The processor may also be in communication with one or more wireless transceivers for wireless data communication. The processor may be capable of being paired to a pneumatic commuting device (e.g., cellphone, PDA, etc.) having wireless Internet connectivity. The processor may be configured to wirelessly connect to one or more personal computing devices in the vicinity of the vehicle, and provide a wireless Internet access point to the one or more personal computing devices based on the wireless connection and the Internet connectivity. | 02-16-2012 |