Patent application number | Description | Published |
20090271531 | ADAPTIVE BANDWIDTH DISTRIBUTION SYSTEM FOR HIGH-PERFORMANCE INPUT/OUTPUT DEVICES WITH VARIABLE THROUGHPUT - A method for issuing shadow requests to manage bandwidth allocation between an application that issues input/output (I/O) operation requests and an I/O device. A bandwidth manager detects the completion of an I/O operation, which includes either a read operation or a write operation. The bandwidth manager calculates a statistical duration for future I/O operations between the application and the I/O device based on throughput statistics related to past I/O operations. The bandwidth manager generates a shadow request for reserving a position in a queue that stores pending I/O requests for the I/O device for a first future I/O operation request from the application and having a duration related to the statistical duration, and inserts the shadow request into the queue. Advantageously, applications that do not make frequent I/O operation requests in advance may still execute I/O operations because bandwidth is reserved for future I/O operation requests via the shadow requests. | 10-29-2009 |
20090271537 | ADAPTIVE BANDWIDTH DISTRIBUTION SYSTEM FOR HIGH-PERFORMANCE INPUT/OUTPUT DEVICES WITH VARIABLE THROUGHPUT - A method for issuing shadow requests to manage bandwidth allocation between an application that issues input/output (I/O) operation requests and an I/O device. A bandwidth manager detects the completion of an I/O operation, which includes either a read operation or a write operation. The bandwidth manager calculates a statistical duration for future I/O operations between the application and the I/O device based on throughput statistics related to past I/O operations. The bandwidth manager generates a shadow request for reserving a position in a queue that stores pending I/O requests for the I/O device for a first future I/O operation request from the application and having a duration related to the statistical duration, and inserts the shadow request into the queue. Advantageously, applications that do not make frequent I/O operation requests in advance may still execute I/O operations because bandwidth is reserved for future I/O operation requests via the shadow requests. | 10-29-2009 |
20090271538 | ADAPTIVE BANDWIDTH DISTRIBUTION SYSTEM FOR HIGH-PERFORMANCE INPUT/OUTPUT DEVICES WITH VARIABLE THROUGHPUT - A method for issuing shadow requests to manage bandwidth allocation between an application that issues input/output (I/O) operation requests and an I/O device. A bandwidth manager detects the completion of an I/O operation, which includes either a read operation or a write operation. The bandwidth manager calculates a statistical duration for future I/O operations between the application and the I/O device based on throughput statistics related to past I/O operations. The bandwidth manager generates a shadow request for reserving a position in a queue that stores pending I/O requests for the I/O device for a first future I/O operation request from the application and having a duration related to the statistical duration, and inserts the shadow request into the queue. Advantageously, applications that do not make frequent I/O operation requests in advance may still execute I/O operations because bandwidth is reserved for future I/O operation requests via the shadow requests. | 10-29-2009 |
Patent application number | Description | Published |
20080253928 | Substrate for Biochip and Method for Manufacturing Substrate for Biochip - A substrate for biochips has a substrate surface having a reaction region capable of reacting with biological substances and a non-reaction region not reacting with the biological substances, sunken bottomed wells formed in the substrate surface, and a layer of a material capable of reacting with the biological substances having a surface exposed only at the bottoms of the bottomed wells, the exposed surface forming the reaction region. | 10-16-2008 |
20090060788 | Microfluidic component with a channel filled with nanotubes and method for its production - A microfluidic component comprises at least one channel ( | 03-05-2009 |
20090200165 | USE OF POLYMER REAGENTS TO MODULATE AND CONTROL ELECTROKINETIC FLOWS IN A MICRO- OR NANOFLUIDIC DEVICE - The invention concerns the field of microfluidics and in particular that of electrophoresis on a micro- or nanofluidic device. More particularly, the invention concerns the use of a reactive polymer coating adapted to be submitted to a phase separation under the influence of an external stimulation of chemical or physical type, to modulate the electrokinetic flows (electroosmotic or electrophoretic flows during electrophoresis for example) in a micro- or nanofluidic device. The invention also concerns a method for varying the electrokinetic flows in such a device using said coating, as well as the micro- or nanofluidic devices comprising at least one channel or one capillary tube whereof the inner surface is covered at least partly with such a coating. | 08-13-2009 |
20090221449 | Presentation of Recognition Motifs by a Multivalent Matrix Grafted Onto a Solid Support - The invention relates to a method for preparing a grafted homodetic cyclopeptide forming a frame defining two surfaces, one surface being known as the upper surface and the other surface being known as the lower surface, both surfaces being grafted, characterized in the a linear peptide is synthesized, said synthesis is being carried out on modified amino acids or not, some of which include orthogonal protector groups, intramolecular cyclization of the protected linear peptide thus obtained is performed, all or part of the orthogonal protector groups are substituted by a protected precursor, and at least one molecule of therapeutic interest is grafted on one and/or the other surface of the frame by means of an oxime link. | 09-03-2009 |
20100288727 | METHOD FOR MANUFACTURING SUBSTRATE FOR BIOCHIP - A substrate for biochips is manufactured so that the substrate has a substrate surface having a reaction region capable of reacting with biological substances and a non-reaction region not reacting with the biological substances, sunken bottomed wells formed in the substrate surface, and a layer of a material capable of reacting with the biological substances having a surface exposed only at the bottoms of the bottomed wells, the exposed surface forming the reaction region. | 11-18-2010 |
20130149196 | Method for Functionalising Fluid Lines Contained in a Micromechanical Device, Micromechanical Device Including Functionalised Lines, and Method for Manufacturing Same - The present invention relates to a method for functionalising fluid lines ( | 06-13-2013 |
20140322767 | DROPLET MICROREACTOR - The present invention relates to a droplet microreactor, i.e. a microreactor consisting of a droplet of a specific liquid, the microreactor being wall-less, wherein the interface of the specific liquid with the ambient environment and with the support on which the droplet is deposited defines the limits of the microreactor. The microreactor is characterized in that it consists of a droplet comprising at least one ionic liquid. The present invention also relates to methods for carrying out chemical or biochemical reactions and/or mixes using said droplet microreactor, and also to a lab-on-chip comprising a microreactor according to the invention. | 10-30-2014 |
Patent application number | Description | Published |
20130334651 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 12-19-2013 |
20150221723 | MATCHING OF TRANSISTORS - The present invention relates to a pair of transistors wherein each transistor of said transistor pair is made of several sub-transistors, and each sub-transistor of a transistor has a sub-transistor channel length and has a sub-transistor channel width, said sub-transistor channel length being substantially equal to the transistor channel length, and said sub-transistor channel width being smaller than the transistor channel width, so that the sum of the sub-transistor channel widths of the sub-transistors of a transistor is substantially equal to the channel width of said transistor, wherein each sub-transistor ( | 08-06-2015 |
20150279861 | DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES - Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material. | 10-01-2015 |
Patent application number | Description | Published |
20140061798 | MICROELECTRONIC DEVICE WITH ISOLATION TRENCHES EXTENDING UNDER AN ACTIVE AREA - A microelectronic device including:
| 03-06-2014 |
20140231916 | Transistor with coupled gate and ground plane - An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer. | 08-21-2014 |
20140302661 | CONTACT ISOLATION SCHEME FOR THIN BURIED OXIDE SUBSTRATE DEVICES - A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material. | 10-09-2014 |
20140312461 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 10-23-2014 |
20150044841 | METHOD FOR FORMING DOPED AREAS UNDER TRANSISTOR SPACERS - Method for fabricating a transistor comprising the steps consisting of:
| 02-12-2015 |
20150056734 | METHOD FOR SEPARATION BETWEEN AN ACTIVE ZONE OF A SUBSTRATE AND ITS BACK FACE OR A PORTION OF ITS BACK FACE - A Method for making a separation between an active zone of a substrate located on its front face from a given portion of the substrate located on its back face, wherein trenches and cavities wider than the trenches are formed to extend said trenches, such that at least one given cavity formed to extend a given trench is adjacent to another cavity, and when the cavities have been filled with a given material, they form a separation zone between said active zone and a given portion of the substrate that will be removed later. | 02-26-2015 |
20150179453 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 06-25-2015 |
20150294903 | METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS - A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region. | 10-15-2015 |
20150294904 | METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS - A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench. | 10-15-2015 |
20150340275 | METHOD OF PRODUCING A MICROELECTRONIC DEVICE IN A MONOCRYSTALLINE SEMICONDUCTOR SUBSTRATE WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER AN ACTIVE REGION - A method of producing a microelectronic device in a substrate including a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, the method including: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device; chemical vapor etching the second semiconductor layer, at a level of a bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region; filling the trench and the etched part of the second semiconductor layer with a dielectric material. | 11-26-2015 |