Patent application number | Description | Published |
20080229145 | Method and system for soft error recovery during processor execution - A system for soft error recovery used during processor execution. The system may include a microprocessor, processor, controller, or the like. The system may also include a pipeline to reduce the cycle time of the processor, and a write-back stage within the pipeline. The system may further include an error-correcting code stage before the write-back stage that checks a value to be written by the processor for any error. The error-correcting code stage may correct any error in the value, and the pipeline may lack a recovery unit pipeline. | 09-18-2008 |
20080256383 | METHOD AND SYSTEM OF PREDICTING MICROPROCESSOR LIFETIME - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 10-16-2008 |
20080313509 | METHOD AND APPARATUS FOR PREVENTING SOFT ERROR ACCUMULATION IN REGISTER ARRAYS - A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater than a threshold. | 12-18-2008 |
20090013207 | PREDICTING MICROPROCESSOR LIFETIME RELIABILITY USING ARCHITECTURE-LEVEL STRUCTURE-AWARE TECHNIQUES - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 01-08-2009 |
20090089602 | METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT - A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system. | 04-02-2009 |
20090144669 | METHOD AND ARRANGEMENT FOR ENHANCING PROCESS VARIABILITY AND LIFETIME RELIABILITY THROUGH 3D INTEGRATION - A method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an arrangement for implementing the inventive method. | 06-04-2009 |
20090144678 | METHOD AND ON-CHIP CONTROL APPARATUS FOR ENHANCING PROCESS RELIABILITY AND PROCESS VARIABILITY THROUGH 3D INTEGRATION - A method and on-chip controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. | 06-04-2009 |
20090177919 | DYNAMIC REDUNDANCY FOR MICROPROCESSOR COMPONENTS AND CIRCUITS PLACED IN NONOPERATIONAL MODES - An apparatus for implementing dynamic redundancy for a microprocessor system includes a plurality of microprocessor components, each of which is capable of being selectively placed in a non-operational mode while one or more other of the microprocessor components remain in an operational mode, and then subsequently restored from the non-operational mode back to the operational mode, the spare microprocessor component configured to be switched from the non-operational mode to the operational mode whenever one of the plurality of the microprocessor components is placed in the non-operational mode, and wherein the spare microprocessor component is configured to be switched back to the non-operational mode whenever each of the microprocessor components are in the operational mode; and multiplexing circuitry configured to map the use of the microprocessor components and the spare microprocessor component with respect to the operational mode and the non-operational mode. | 07-09-2009 |
20090178051 | METHOD FOR IMPLEMENTING DYNAMIC LIFETIME RELIABILITY EXTENSION FOR MICROPROCESSOR ARCHITECTURES - A method for implementing dynamic lifetime reliability extension for microprocessor architectures having a plurality of primary resources and a secondary resource pool of one or more secondary resources includes configuring a resource operational mode controller to selectively switch of the primary and secondary resources between an operational mode and a non-operational mode, wherein the non-operational mode corresponds to a lifetime extension process; configuring a resource mapper associated with the secondary resource pool and in communication with the resource operational mode controller to map a secondary resource placed into the operational mode to a corresponding primary resource placed into the non-operational mode; and configuring a transaction decoder to receive incoming transaction requests and direct the requests to one of a primary resource in the operational mode and a secondary resource in the operational mode, the secondary resource mapped to an associated primary resource placed in the non-operational mode. | 07-09-2009 |
20100015732 | SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP - Base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet, which provides the same functionality as one of the at least one non-functional chiplet is designed to provide, is vertically stacked. The at least one repair semiconductor chiplet provides the functionality that the at least one non-functional chiplet is designed to provide to the base semiconductor chip. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. In case a first attempt to repair the base semiconductor chip by stacking repair semiconductor chips is unsuccessful, additional repair semiconductor chips may be subsequently stacked to fully repair the base semiconductor chip. | 01-21-2010 |
20120030481 | Measuring Data Switching Activity in a Microprocessor - A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity. | 02-02-2012 |
20130128684 | REDUCED LEAKAGE BANKED WORDLINE HEADER - A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication. | 05-23-2013 |
20140159803 | SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP - In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. | 06-12-2014 |
20150076908 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 03-19-2015 |
20150077170 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 03-19-2015 |
20150081123 | PREDICTIVELY TURNING OFF A CHARGE PUMP SUPPLYING VOLTAGE FOR OVERDRIVING GATES OF THE POWER SWITCH HEADER IN A MICROPROCESSOR WITH POWER GATING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit. | 03-19-2015 |
20150081125 | PREDICTIVELY TURNING OFF A CHARGE PUMP SUPPLYING VOLTAGE FOR OVERDRIVING GATES OF THE POWER SWITCH HEADER IN A MICROPROCESSOR WITH POWER GATING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit. | 03-19-2015 |
20150082065 | ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES - A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source. | 03-19-2015 |
20150082066 | ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request. | 03-19-2015 |
20150082069 | ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES - A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source. | 03-19-2015 |
20150082070 | ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request. | 03-19-2015 |