| Patent application number | Description | Published |
|---|
| 20140117493 | ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY - Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures. | 05-01-2014 |
| 20140246676 | BIPOLAR DEVICE HAVING A MONOCRYSTALLINE SEMICONDUCTOR INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION - A bipolar device with an entirely monocrystalline intrinsic base to extrinsic base link-up region. To form the device, a first extrinsic base layer, which is amorphous or polycrystalline, is deposited such that it contacts an edge portion of a monocrystalline section of an intrinsic base layer through an opening in a dielectric layer. A second extrinsic base layer is deposited on the first. An anneal is performed, either before or after deposition of the second extrinsic base layer, so that the extrinsic base layers are monocrystalline. An opening is formed through the extrinsic base layers to a dielectric landing pad aligned above a center portion of the monocrystalline section of the intrinsic base layer. The dielectric landing pad is removed and a semiconductor layer is grown epitaxially on exposed monocrystalline surfaces of the extrinsic and intrinsic base layers, thereby forming the entirely monocrystalline intrinsic base to extrinsic base link-up region. | 09-04-2014 |
| 20140264341 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer. | 09-18-2014 |
| 20140353725 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE BY FORMING MONOCRYSTALLINE SEMICONDUCTOR LAYERS ON A DIELECTRIC LAYER OVER ISOLATION REGIONS - Disclosed are devices and methods of forming the devices wherein pair(s) of first openings are formed through a dielectric layer and a first semiconductor layer into a substrate and, within the substrate, the first openings of each pair are expanded laterally and merged to form a corresponding trench. Dielectric material is deposited, filling the upper portions of the first openings and creating trench isolation region(s). A second semiconductor layer is deposited and second opening(s) are formed through the second semiconductor and dielectric layers, exposing monocrystalline portion(s) of the first semiconductor layer between the each pair of first openings. A third semiconductor layer is epitaxially deposited with a polycrystalline section on the second semiconductor layer and monocrystalline section(s) on the exposed monocrystalline portion(s) of the first semiconductor layer. A crystallization anneal is performed and a device (e.g., a bipolar device) is formed incorporating the resulting monocrystalline second and third semiconductor layers. | 12-04-2014 |
| 20140361300 | BIPOLAR DEVICE HAVING A MONOCRYSTALLINE SEMICONDUCTOR INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION - Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers. A semiconductor layer is then formed by epitaxial deposition on the exposed monocrystalline surfaces, thereby forming the entirely monocrystalline link-up region. | 12-11-2014 |
| 20140368227 | IN-LINE MEASUREMENT OF TRANSISTOR DEVICE CUT-OFF FREQUENCY - A test circuit within a semiconductor wafer that measures a cut-off frequency for a transistor device under test may include a radio frequency source, located within a region of the wafer, that generates a radio frequency signal. A biasing circuit, also located within the region, may provide a current bias setting to the transistor device under test. The biasing circuit receives the radio frequency signal and applies a buffered radio frequency signal to the transistor device under test. The biasing circuit generates a buffered output signal based on the transistor device under test generating a first output signal in response to receiving the applied buffered radio frequency signal. An rf power detector, within the region, receives the first output signal and the radio frequency signal, and generates an output voltage signal, wherein the cut-off frequency of the transistor device under test is determined from the generated output voltage signal. | 12-18-2014 |
| 20150021738 | BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer. | 01-22-2015 |
| 20150035011 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE - Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer. | 02-05-2015 |
| 20150041956 | ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY - Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures. | 02-12-2015 |
| 20150053982 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE - Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer. | 02-26-2015 |
