Patent application number | Description | Published |
20130025926 | CIRCUIT SUBSTRATE - A circuit substrate having a base layer, a patterned conductive layer, a dielectric layer and a conductive block is provided. The patterned conductive layer is disposed on the base layer and having an inner pad. The dielectric layer is disposed on the base layer and covering the patterned conductive layer. The conductive block penetrates the dielectric layer, the conductive block being substantially coplanar with the dielectric layer and connecting the inner pad. | 01-31-2013 |
20130059453 | INTEGRATED CIRCUITS - An integrated circuit for accessing a universal serial bus (USB) device via a USB 3.0 receptacle is provided. The integrated circuit includes a plurality of pins and a controlling unit. The pins include a first group for coupling to a first pair of differential pins of the USB receptacle, a second group for coupling to a second pair of differential pins of the USB receptacle, a third group for coupling to a third pair of differential pins to the USB receptacle, a ground pin, a first and second power pins. The second group is disposed between the first and third groups. The controlling unit controls the plurality of pins to receive or transmit the USB 2.0 or USB 3.0 signals. | 03-07-2013 |
20130076404 | LOW VOLTAGE DIFFERENTIAL SIGNAL DRIVING CIRCUIT AND ELECTRONIC DEVICE COMPATIBLE WITH WIRED TRANSMISSION - A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal). In accordance with the low-high (or high-low) transition acceleration control signal, the transition accelerator couples the positive (or negative) differential output terminal to a high voltage source and couples the negative (or positive) differential output terminal to a low voltage source to accelerate transition of the differential output signal. | 03-28-2013 |
20130099840 | DUTY ADJUSTMENT CIRCUITS AND SIGNAL GENERATION DEVICES USING THE SAME - A duty adjustment circuit is provided. The duty adjustment circuit is used to adjust a duty cycle of a first driving signal. The duty adjustment circuit includes a filter, a first comparator, and a first duty adjustor. The filter receives a comparison result signal and filters the comparison result signal to generate a duty information signal. The duty information signal indicates a duty cycle of the comparison result signal. The first comparator receives the duty information signal and determines whether a direct-current (DC) level of the duty information signal falls into a predefined voltage range to generate a first adjustment signal. The first duty adjustor receives the first adjustment signal and the first driving signal and adjusts the duty cycle of the first driving signal according to the first adjustment signal. | 04-25-2013 |
20130114173 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device, having a P-type semiconductor substrate set as floating; a first N-well and a second N-well formed in the P-type substrate; a first P-doped region and a second P-doped region formed in the first N-well and the second N-well, respectively. The first N-well and the first P-doped region form a first diode, and the second N-well and the second P-doped region form a second diode. A first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively. A third P-doped region is formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region. | 05-09-2013 |
20130132746 | BRIDGING DEVICE AND POWER SAVING METHOD THEREOF - A bridging device and a power saving method thereof are disclosed. The disclosed bridging device includes a connector, a connection detector and a bridging chip. The connector is operative to connect to a host and includes a power pin and a command pin. The connection detector is coupled to the power pin to determine whether the connector is floating, and, outputs a linked signal when the connection is non-floating. The bridging chip is coupled to the command pin and the connection detector. When the bridging chip receives a power saving command transferred from the host via the command pin and the linked signal transferred from the connection detector, the bridging chip executes a power saving operation. | 05-23-2013 |
20130151731 | USB CHARGING MODULE - An apparatus is provided for charging a Universal Serial Bus (USB) device according to an optimal charging mode. The apparatus includes a charging module that is configured to obtain a descriptor from the USB device upon detection of the USB device on a USB bus. The charging module includes one or more descriptor entries disposed in a memory and a controller. The one or more descriptor entries include descriptor data, for matching the descriptor to a specific descriptor entry, and charging data, that specifies the optimal charging mode for the USB device. The controller is coupled to the memory, and is configured to match the descriptor to the specific descriptor entry, and is configured to initiate the optimal charging mode on the USB bus according to the charging data. | 06-13-2013 |
20130151749 | APPARATUS FOR COUPLING TO A USB DEVICE AND A HOST AND METHOD THEREOF - An apparatus is provided for coupling a Universal Serial Bus (USB) device and a USB host. The apparatus includes a memory and a controller. The memory includes one or more descriptor entries. The controller is configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result. Then the controller enables or disables a link path between the USB host and the USB device according the comparing result. | 06-13-2013 |
20130151881 | BRIDGING DEVICE AND POWER SAVING METHOD THEREOF - A bridging device and a power saving method thereof are disclosed. When a bridging chip of the bridging device receives a power saving command transferred from a host and thereby enters a power saving state, a voltage converter of the bridging device is disabled accordingly and a selection circuit selects to couple a bus voltage to the bridging chip to power the bridging chip. The bus voltage is transferred from the host through a power pin of a connector of the bridging device. The connector is coupled to the host. | 06-13-2013 |
20130179604 | DATA TRANSMISSION METHODS AND HUB DEVICES UTILIZING THE SAME - A hub device includes an upstream port, multiple downstream ports, a first and a second sub-hub module, a data-format detector, a transaction translator, and a controller. The upstream port is coupled to a host device supporting a first and/or a second data format. Each downstream port is coupled to one of a plurality of slave devices supporting a first and/or a second data format. The first sub-hub module supports transmission of data in the first data format. The second sub-hub module supports transmission of data in the second data format. The data-format detector detects the data format supported by the host device and the slave devices. The transaction translator transforms the data format between the first data format and the second data format. The controller determines whether to control the transaction translator to perform data-format transformation. | 07-11-2013 |
20130179748 | SYSTEMS AND METHODS FOR ERROR CHECKING AND CORRECTING FOR MEMORY MODULE - Methods for error checking and correcting (ECC) in a memory module including at least one memory unit are provided. The method includes the steps of: receiving input data from the memory unit; performing, by a first ECC module, a first ECC operation to the input data and generating a decoding result which indicates whether decoding was successful; and determining whether to activate a second ECC module to perform a second ECC operation to the input data according to the decoding result, wherein the first and second ECC modules respectively utilize a first method and a second method, wherein the first method applies a ECC with a first fault tolerant quantity for error correction and the second method applies a ECC with a second fault tolerant quantity for error correction, and the second fault tolerant quantity is larger than the first fault tolerant quantity. | 07-11-2013 |
20130187608 | RECHARGEABLE BATTERY MODULE AND BATTERY CHARGING METHOD - A rechargeable battery module including a plurality of battery cells connected in series, a charging transistor, a balancing circuit and a control chip. The charging transistor is operative to convey a charging current to charge the battery cells. Based on voltage levels of the battery cells, the control chip disables the charging transistor and controls the balancing circuit to perform a first stage battery balance process. After finishing the first stage battery balance process, the control chip enables the charging transistor to charge the battery cells again. After being switched to a constant voltage charging mode, the control chip controls the balancing circuit based on the voltage levels of the battery cells to perform a second stage battery balance process. | 07-25-2013 |
20130187609 | RECHARGEABLE BATTERY MODULE AND BATTERY CHARGING METHOD - An embodiment of the invention provides a rechargeable battery module including a battery bank having serial connected battery units, a charging transistor providing a charging current to the battery bank, a balancing circuit for detecting and balancing voltage values of battery units and battery bank and a control chip. When a first voltage value of a first battery unit reaches a charge-off voltage, the control chip estimates a first unbalanced voltage difference between the first voltage and the minimal voltage among battery units. The control chip disables the charging transistor and estimates a second unbalanced voltage difference between voltages of the first battery unit and the battery unit having a minimal voltage. The control chip enables the balancing circuit to balance the first battery unit. When the voltage of the first battery is dropped by a calibration target, the charging transistor is enabled. | 07-25-2013 |
20130187657 | DISCHARGE CURVE CALIBRATION SYSTEM AND CALIBRATION METHOD FOR INITIAL DISCHARGING CURVE OF BATTERY - An embodiment of the invention provides a calibration method for an initial discharging curve of a battery. The method includes: acquiring an initial discharging curve of a battery; measuring a first open circuit voltage at a first time point and a second open circuit voltage at a second time point; according to the initial discharging curve, acquiring a first discharge capacity corresponding to the first open circuit voltage and a second discharge capacity corresponding to the second open circuit voltage according to the initial discharging curve; calculating an ideal discharge capacity according to the first discharge capacity and the second discharge capacity; measuring an real discharge capacity between the first time point and the second time point; determining a total discharge capacity difference according to the ideal discharge capacity and the real discharge capacity to calibrate the initial discharging curve to generate a current discharging curve. | 07-25-2013 |