Vereen
Jerry Darden Vereen, Coral Springs, FL US
Patent application number | Description | Published |
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20120038213 | NON-CHARGING BATTERY BACKUP UNIT (BBU) - A battery backup unit (BBU) includes a housing, at least one battery compartment in the housing with an output terminal, a DC input, a DC output, a path from the DC input to the DC output, circuitry for selectively connecting the output terminal to the path, which circuitry includes a switch, and a controller configured to detect a condition of the path and selectively control the switch to connect the output terminal to the path when the condition is detected, the BBU being incapable of charging batteries in the at least one battery compartment. The path from the DC input to the DC output may include a DC/DC step up converter to help maintain a constant output voltage. | 02-16-2012 |
John Vereen, Alexandria, VA US
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20140368821 | HEAT SENSITIVE TAMPER INDICATING MARKINGS - The present invention relates to the field of heat sensitive optically variable inks and tamper indicating markings obtained thereof. The present invention relates to the field of irreversible changes in color and/or changes in structure upon a tampering attempt against articles or items comprising said tamper indicating markings through the use of temperature variation. In particular, the present invention provides optically variable ink compositions comprising a plurality of optically variable pigment particles and a plurality of thermally expandable spheres; tamper indicating marking comprising the optically variable ink compositions described herein; their uses as a proof of an illegal action as well as methods for detecting a tampering activity of a marking including the optically variable ink composition described herein. | 12-18-2014 |
Lidia Vereen, San Ramon, CA US
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20130082228 | Memory Device Using Multiple Tunnel Oxide Layers - A memory element (ME) including at least one layer of conductive metal oxide (CMO) that includes mobile oxygen ions and including at least two layers of insulating metal oxide (IMO) is disclosed. In one configuration a layer of IMO that is directly in contact with a CMO layer is specifically selected so that a material of the IMO layer is non-reactive with a material of the CMO. In another configuration, at least one pair of adjacent IMO layers are made from materials having different band gaps operative to an generate an internal electric field positioned in the layers and present in the at least two adjacent IMO layers in the absence of electrical power. The internal electric field can be a static electric field. The IMO and/or CMO layers can be deposited in part or in whole using ALD, PEALD, or nano-deposition. The ME can be formed BEOL. | 04-04-2013 |
20130207066 | PLANAR RESISTIVE MEMORY INTEGRATION - In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void. | 08-15-2013 |
20130210211 | Vertical Cross-Point Memory Arrays - A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F | 08-15-2013 |
20140231741 | PLANAR RESISTIVE MEMORY INTEGRATION - In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void. | 08-21-2014 |
William Vereen, Thomasville, GA US
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20100043116 | Breathable, Vented, Flame-Resistant Shirt - A flame-resistant shirt is described that has vents to facilitate heat release and air circulation while preserving flame-resistant qualities. The shirt has a standard front half, but a back half which includes a cape portion with openings to provide ventilation across the wearer's back. | 02-25-2010 |
William C. Vereen, Thomasville, GA US
Patent application number | Description | Published |
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20090205101 | Shirt with Reinforced Front - A shirt is described that uses a double layer of fabric, strategically located across its front to protect the torso of the wearer. | 08-20-2009 |
20110271419 | SHIRT WITH REINFORCED FRONT - A fire resistant shirt is described that is constructed from two or more layers of fire resistant fabric strategically located across the front portion of the shirt to protect the torso of the wearer. | 11-10-2011 |