| Patent application number | Description | Published |
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| 20100088658 | METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION - In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed. | 04-08-2010 |
| 20100180243 | Method of Performing Timing Analysis on Integrated Circuit Chips with Consideration of Process Variations - A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA). | 07-15-2010 |
| 20100211922 | Method of Performing Statistical Timing Abstraction for Hierarchical Timing Analysis of VLSI circuits - A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction. | 08-19-2010 |
| 20110055793 | TIMING CLOSURE ON MULTIPLE SELECTIVE CORNERS IN A SINGLE STATISTICAL TIMING RUN - An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks. | 03-03-2011 |
| 20120084066 | SYSTEM AND METHOD FOR EFFICIENT MODELING OF NPSKEW EFFECTS ON STATIC TIMING TESTS - A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result. | 04-05-2012 |
| 20120117527 | PERFORMING STATISTICAL TIMING ANALYSIS WITH NON-SEPARABLE STATISTICAL AND DETERMINISTIC VARIATIONS - In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner. | 05-10-2012 |
| 20120124534 | System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times - A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack. | 05-17-2012 |
| 20130018617 | INTEGRATING MANUFACTURING FEEDBACK INTO INTEGRATED CIRCUIT STRUCTURE DESIGNAANM Buck; Nathan C.AACI UnderhillAAST VTAACO USAAGP Buck; Nathan C. Underhill VT USAANM Dreibelbis; Brian M.AACI UnderhillAAST VTAACO USAAGP Dreibelbis; Brian M. Underhill VT USAANM Dubuque; John P.AACI JerichoAAST VTAACO USAAGP Dubuque; John P. Jericho VT USAANM Foreman; Eric A.AACI FairfaxAAST VTAACO USAAGP Foreman; Eric A. Fairfax VT USAANM Habitz; Peter A.AACI HinesburgAAST VTAACO USAAGP Habitz; Peter A. Hinesburg VT USAANM Hemmett; Jeffrey G.AACI St. GeorgeAAST VTAACO USAAGP Hemmett; Jeffrey G. St. George VT USAANM Venkateswaran; NatesanAACI Hopewell JunctionAAST NYAACO USAAGP Venkateswaran; Natesan Hopewell Junction NY USAANM Visweswariah; ChandramouliAACI Croton-on-HudsonAAST NYAACO USAAGP Visweswariah; Chandramouli Croton-on-Hudson NY USAANM Wang; XiaoyueAACI KanataAACO CAAAGP Wang; Xiaoyue Kanata CAAANM Zolotov; VladmimirAACI Putnam ValleyAAST NYAACO USAAGP Zolotov; Vladmimir Putnam Valley NY US - Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings. | 01-17-2013 |
| 20130031523 | SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS - Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor. | 01-31-2013 |
| 20130036395 | EFFICIENT SLACK PROJECTION FOR TRUNCATED DISTRIBUTIONS - Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset. | 02-07-2013 |
| 20130104092 | METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR PERFORMING A PARAMETERIZED STATISTICAL STATIC TIMING ANALYSIS (SSTA) OF AN INTEGRATED CIRCUIT TAKING INTO ACCOUNT SETUP AND HOLD MARGIN INTERDEPENDENCE - In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree. | 04-25-2013 |
| 20130145333 | STATISTICAL CLOCK CYCLE COMPUTATION - Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA. | 06-06-2013 |
| 20130159953 | PERFORMING STATISTICAL TIMING ANALYSIS WITH NON-SEPARABLE STATISTICAL AND DETERMINISTIC VARIATIONS - In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner. | 06-20-2013 |
| 20130179852 | SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS - Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor. | 07-11-2013 |
| 20140096100 | METHOD OF SHARING AND RE-USING TIMING MODELS IN A CHIP ACROSS MULTIPLE VOLTAGE DOMAINS - A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts. | 04-03-2014 |
| 20140115552 | SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS - Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor. | 04-24-2014 |
| 20140123086 | PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form. | 05-01-2014 |
| 20140123089 | MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING - Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively. | 05-01-2014 |
| 20140123091 | HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell. | 05-01-2014 |
| 20140123095 | MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING - Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively. | 05-01-2014 |
| 20140173543 | PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form. | 06-19-2014 |
| 20140298280 | REDUCING RUNTIME AND MEMORY REQUIREMENTS OF STATIC TIMING ANALYSIS - Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis. | 10-02-2014 |
| 20140359547 | HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell. | 12-04-2014 |
| 20150082260 | MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING - Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively. | 03-19-2015 |
| 20150242554 | PARTIAL PARAMETERS AND PROJECTION THEREOF INCLUDED WITHIN STATISTICAL TIMING ANALYSIS - Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter. | 08-27-2015 |
