Patent application number | Description | Published |
20100270645 | THIN-FILM CAPACITOR STRUCTURES EMBEDDED IN SEMICONDUCTOR PACKAGES AND METHODS OF MAKING - Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages. | 10-28-2010 |
20100270646 | THIN-FILM CAPACITOR STRUCTURES EMBEDDED IN SEMICONDUCTOR PACKAGES AND METHODS OF MAKING - Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages. | 10-28-2010 |
20120228754 | CHIP-LAST EMBEDDED INTERCONNECT STRUCTURES AND METHODS OF MAKING THE SAME - The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options. | 09-13-2012 |
20130107485 | INTERCONNECT STRUCTURES AND METHODS OF MAKING THE SAME | 05-02-2013 |
20130119555 | Through-Package-Via (TPV) Structures On Inorganic Interposer And Methods For Fabricating Same - The present invention generally relates to the use of glass as the interposer material with the surface of the interposer and/or the walls of through vias in being coated by a stress relief barrier that provides thermal expansion and contraction stress relief and better metallization capabilities. The present invention discloses ways in that a stress relief barrier can be used to reduce the effects of stress caused by the different CTEs while also, in some applications, acting as an adhesion promoter between the metallization and the interposer. The stress relief barrier acts to absorb some of the stress caused by the different CTEs and promotes better adhesion for the conductive metal layer, thus helping to increase reliability while also providing for smaller designs. | 05-16-2013 |
20140145328 | INTERCONNECT ASSEMBLIES AND METHODS OF MAKING AND USING SAME - The various embodiments of the present invention provide fine pitch, chip-to-substrate hybrid interconnect assemblies, as well as methods of making and using the assemblies. The hybrid assemblies generally include a semiconductor having a die pad disposed thereon, a substrate having a substrate pad disposed thereon, and a polymer layer disposed between the surface of the die pad and the surface of the substrate pad. In addition, at least a portion of the surface of the die pad is metallically bonded to at least a portion of the surface of the substrate pad and at least a portion of the surface of the die pad is chemically bonded to at least a portion of the surface of the substrate pad. | 05-29-2014 |
20140347157 | MAGNETIC DEVICE UTILIZING NANOCOMPOSITE FILMS LAYERED WITH ADHESIVES - Exemplary embodiments provide a nanomagnetic structure and method of making the same, comprising a device substrate, a plurality of nanomagnetic composite layers disposed on the device substrate, wherein an adhesive layer is interposed between each of the plurality of nanomagnetic composite layers. Metal windings are integrated within the plurality of nanomagnetic composite layers to form an inductor core, wherein the nanomagnetic structure has a thickness ranging from about 5 to about 100 microns. | 11-27-2014 |
20160111380 | NEW STRUCTURE OF MICROELECTRONIC PACKAGES WITH EDGE PROTECTION BY COATING - Disclosed herein are edge-coated microelectronic packages comprising a microelectronic package having a top, a bottom, and an exposed edge, and a coating comprising a polymer, wherein the microelectronic package comprises a glass substrate, and wherein the coating covers at least a portion of the top, at least a portion of the bottom, and at least a portion of the exposed edge of the microelectronic package. Also disclosed herein are methods of making and using edge-coated microelectronic packages. | 04-21-2016 |
20160113108 | PACKAGE-LEVEL ELECTROMAGNETIC INTERFERENCE SHIELDING STRUCTURES FOR A SUBSTRATE - A electromagnetic interference shielding device is disclosed having a first substrate one or more surfaces. One or more laminates are operatively attached to the one or more surfaces of the first substrate. A cavity is provided that is defined by the first substrate and its corresponding one or more laminates and at least one inner lateral portion. The cavity is operable to receive one or more microelectromechanical system (MEMS) components. A first conductive structure integrally formed with a trench or via array of the substrate spans a thickness defined by one or more of surfaces of the first substrate, the first conductive structure operable to shield electromagnetic interference between MEMS components assembled with the first substrate. | 04-21-2016 |