Patent application number | Description | Published |
20090066555 | A/D Converter Comprising a Voltage Comparator Device - The present invention discloses an analogue-to-digital converter comprising at least two voltage comparator devices. Each of the voltage comparator devices comprises a differential structure of transistors and is arranged for being fed with a same input signal and for generating an own internal voltage reference by means of an imbalance in the differential structure, said two internal voltage references being different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of the input signal. | 03-12-2009 |
20090195424 | A/D Converter Comprising a Voltage Comparator Device - The present invention is related to an analogue-to-digital (A/D) converter comprising at least two voltage comparator devices. Each of the voltage comparator devices is arranged for being fed with a same input signal and for generating an own internal voltage reference. The two internal voltage references are different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of said input signal. | 08-06-2009 |
20100283649 | Sigma-delta-based analog-to-digital converter - An analog to digital converting device is proposed for generating a digital output signal of an RF analog input signal. The device comprises a first analog to digital converter stage, a mixer, a second analog to digital converter stage and a digital filter. The first analog to digital converter stage generates a first and a second output signal. The first output signal is inputted in the filtering means. The second output signal is being down-converted to a signal with an intermediate frequency or DC. Thereafter, this down-converted signal is being fed to the second analog to digital converter stage. The digital output signal of this second stage is further processed together with the first digital output signal in the digital filter to a digital signal representative of the analog input signal. | 11-11-2010 |
20100328120 | Comparator Based Asynchronous Binary Search A/D Conveter - The present invention is related to an analog-to-digital converter circuit ( | 12-30-2010 |
20110102011 | METHOD AND DEVICE FOR TESTING TSVS IN A 3D CHIP STACK - A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry. | 05-05-2011 |
20120025841 | CAPACITANCE MEASUREMENT IN MICROCHIPS - A measurement system for determining the capacitance of a device-under-test in an integrated circuit is disclosed. In one aspect, the measurement system has a reference circuit and a test circuit. Each circuit has first and second diodes that are switched in accordance with a clock cycle to charge and discharge the associated circuit. A method takes average current measurements for each circuit at one voltage level and processes them so that the capacitance of a device-under-test connected to the test circuit can accurately and reliably be determined. Two voltage levels may be used and adjustments are made for voltage threshold of the diodes and also their resistance. | 02-02-2012 |
20120127559 | HOLOGRAPHIC VISUALIZATION SYSTEM COMPRISING A HIGH DATA REFRESH RATE DND DRIVER ARRAY - A DND chip is disclosed. In one aspect, the chip includes a 2D DND array of DND elements logically arranged in rows and columns, and a DND driver architecture for actuating the DND elements. The DND driver has a set of first drive lines along the rows and a set of second drive lines along the columns, a set of first line drivers for each biasing one line from the set of first drive lines and a set of second line drivers for each biasing a line from the set of second drive lines. A plurality of second line drivers are spatially grouped together to serve a block of DND elements, and that plurality of second line drivers are spatially covered substantially completely by at least some DND elements of the block of DND elements. A holographic visualization system including the DND chip is provided. | 05-24-2012 |
20120305542 | Oven Controlled MEMS Oscillator Device - A system is disclosed that includes an oven and a micromechanical oscillator inside the oven configured to oscillate at a predetermined frequency at a predetermined temperature, where the predetermined frequency is based on a temperature dependency and at least one predetermined property. The system further includes an excitation mechanism configured to excite the micromechanical oscillator to oscillate at the predetermined frequency and a temperature control loop configured to detect a temperature of the micromechanical oscillator using resistive sensing, determine whether the temperature of the micromechanical oscillator is within a predetermined range of the predetermined temperature based on the temperature dependency and the at least one predetermined property in order to minimize frequency drift, and adapt the temperature of the micromechanical oscillator to remain within the predetermined range. The system further includes a frequency output configured to output the predetermined frequency of the micromechanical oscillator. | 12-06-2012 |
20130187669 | Calibration of Micro-Mirror Arrays - A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use. | 07-25-2013 |
20140368920 | Micro-Mirror Arrays - Micro-mirror arrays configured for use in a variable focal length lens are described herein. An example variable focal length lens comprises a micro-mirror array having a plurality of micro-mirror element arranged in at least a first section and a second section. Each micro-mirror element has a tilt axis and comprises, on each of two opposing sides of the tilt axis, (i) at least one actuation electrode, (ii) at least one measurement electrode, and (iii) at least one stopper. Additionally, each micro-mirror element in the first section has a first tilt axis range, and each micro-mirror element in the second section has a second tilt axis range, with the first tilt axis range being less than the second tilt axis range. | 12-18-2014 |
20140372057 | METHOD AND SYSTEM FOR MEASURING CAPACITANCE DIFFERENCE BETWEEN CAPACITIVE ELEMENTS - Methods and systems for measuring capacitance difference are disclosed. In one aspect, first and second capacitive elements are connected between voltage receiving nodes for receiving first and second DC voltages and nodes connectable to a third DC voltage via a first, resp. second switch. Further, in a first phase, a voltage difference is applied to charge the capacitive elements and the switches are alternately closed. First resulting currents are measured. Further, in a second phase, the first and second DC voltages are applied alternatingly and the switches are alternately closed. Second resulting currents are measured. The capacitance difference can be determined from the first and second resulting currents. | 12-18-2014 |