Patent application number | Description | Published |
20160093356 | Methods of Reading and Writing Data in a Thyristor Random Access Memory - A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array. | 03-31-2016 |
20160093357 | Methods of Retaining and Refreshing Data in a Thyristor Random Access Memory - A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein. | 03-31-2016 |
20160093358 | Power Reduction in Thyristor Random Access Memory - A volatile memory array using vertical thyristors is disclosed together with methods of reducing power consumption in such arrays. | 03-31-2016 |
20160093362 | Two-Transistor SRAM Circuit and Methods of Fabrication - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 03-31-2016 |
20160093367 | Cross-Coupled Thyristor SRAM Circuits and Methods of Operation - A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby. | 03-31-2016 |
20160093368 | Six-Transistor SRAM Circuits and Methods of Operation - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 03-31-2016 |
20160093369 | Write Assist SRAM Circuits and Methods of Operation - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 03-31-2016 |
20160093607 | Six-Transistor SRAM Semiconductor Structures and Methods of Fabrication - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 03-31-2016 |
20160093622 | Cross-Coupled Thyristor SRAM Semiconductor Structures and Methods of Fabrication - A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby. | 03-31-2016 |
20160093623 | Two-Transistor SRAM Semiconductor Structure and Methods of Fabrication - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 03-31-2016 |
20160093624 | Thyristor Volatile Random Access Memory and Methods of Manufacture - A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array. | 03-31-2016 |