Patent application number | Description | Published |
20120080807 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 04-05-2012 |
20120091582 | MICROELECTRONIC ASSEMBLIES HAVING COMPLIANCY AND METHODS THEREFOR - A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces. | 04-19-2012 |
20120133057 | EDGE CONNECT WAFER LEVEL STACKING - A stacked microelectronic assembly includes a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly. Each stacked subassembly includes at least a respective first microelectronic element having a face and a respective second microelectronic element having a face overlying and parallel to a face of the first microelectronic element. Each of the first and second microelectronic elements has edges extending away from the respective face. A plurality of traces at the respective face extend about at least one respective edge. Each of the first and second stacked subassemblies includes contacts connected to at least some of the plurality of traces. Bond wires conductively connect the contacts of the first stacked subassembly with the contacts of the second stacked subassembly. | 05-31-2012 |
20120153443 | PACKAGED SEMICONDUCTOR CHIPS WITH ARRAY - A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device. | 06-21-2012 |
20120181658 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape. | 07-19-2012 |
20120199925 | BSI IMAGE SENSOR PACKAGE WITH EMBEDDED ABSORBER FOR EVEN RECEPTION OF DIFFERENT WAVELENGTHS - A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has an opening overlying at least one of first and second light sensing elements, the semiconductor region having a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face. A light-absorbing material overlies the semiconductor region within the opening above at least one of the light sensing elements such that the first and second light sensing elements receive light of substantially the same intensity. | 08-09-2012 |
20120199926 | BSI IMAGE SENSOR PACKAGE WITH VARIABLE-HEIGHT SILICON FOR EVEN RECEPTION OF DIFFERENT WAVELENGTHS - A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face such that the first and second light sensing elements receive light of substantially the same intensity. A dielectric region is provided at least substantially filling a space of the semiconductor region adjacent at least one of the light sensing elements. The dielectric region may include at least one light guide. | 08-09-2012 |
20120273933 | THREE-DIMENSIONAL SYSTEM-IN-A-PACKAGE - A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements. | 11-01-2012 |
20120313207 | 3D Integration Microelectronic Assembly For Integrated Circuit Devices And Method Of Making Same - A microelectronic assembly for packaging/encapsulating IC devices, which includes a crystalline substrate handler having opposing first and second surfaces and a cavity formed into the first surface, a first IC device disposed in the cavity and a second IC device mounted to the second surface, and a plurality of interconnects formed through the crystalline substrate handler. Each of the interconnects includes a hole formed through the crystalline substrate handler from the first surface to the second surface, a compliant dielectric material disposed along the hole's sidewall, and a conductive material disposed along the compliant dielectric material and extending between the first and second surfaces. The compliant dielectric material insulates the conductive material from the sidewall. The second IC device, which can be an image sensor, is electrically coupled to the conductive materials of the plurality of interconnects. The first IC can be a processor for processing the signals from the image sensor. | 12-13-2012 |
20120313209 | 3D Integrated Microelectronic Assembly With Stress Reducing Interconnects And Method Of Making Same - A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handier with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element. | 12-13-2012 |
20120313255 | 3D Integration Microelectronic Assembly For Integrated Circuit Devices And Method Of Making Same - A 3D interposer (and method of making same) that includes a crystalline substrate handler having opposing first and second surfaces, with a cavity formed into the first surface. A layer of insulation material is formed on the surface of the handler that defines the cavity. The cavity is filled with a compliant dielectric material. A plurality of electrical interconnects is formed through the interposer. Each electrical interconnect includes a first hole formed through the crystalline substrate handler extending from the second surface to the cavity, a second hole formed through the compliant dielectric material so as to extend from and be aligned with the first hole, a layer of insulation material formed along a sidewall of the first hole, and conductive material extending through the first and second holes. | 12-13-2012 |
20130010441 | MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION - A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure. | 01-10-2013 |
20130020665 | Low Stress Cavity Package For Back Side Illuminated Image Sensor, And Method Of Making Same - An image sensor package includes an image sensor chip and crystalline handler. The image sensor chip includes a substrate, and a plurality of photo detectors and contact pads at the front surface of the substrate. The crystalline handler includes opposing first and second surfaces, and a cavity formed into the first surface. A compliant dielectric material is disposed in the cavity. The image sensor front surface is attached to the crystalline substrate handler second surface. A plurality of electrical interconnects each include a hole aligned with one of the contact pads, with a first portion extending from the second surface to the cavity and a second portion extending through the compliant dielectric material, a layer of insulation material formed along a sidewall of the first portion of the hole, and conductive material extending through the first and second portions of the hole and electrically coupled to the one contact pad. | 01-24-2013 |
20130056844 | Stepped Package For Image Sensor And Method Of Making Same - An image sensor package includes a crystalline handler having opposing first and second surfaces, and a cavity formed into the first surface. At least one step extends from a sidewall of the cavity, wherein the cavity terminates in an aperture at the second surface. A cover is mounted to the second surface and extends over and covers the aperture. The cover is optically transparent to at least one range of light wavelengths. A sensor chip is disposed in the cavity and mounted to the at least one step. The sensor chip includes a substrate with front and back opposing surfaces, a plurality of photo detectors formed at the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the photo detectors. | 03-07-2013 |
20130065390 | CHIPS HAVING REAR CONTACTS CONNECTED BY THROUGH VIAS TO FRONT CONTACTS - A method of fabricating a microelectronic unit can include providing a semiconductor element having front and rear surfaces, a plurality of conductive pads each having a top surface exposed at the front surface and a bottom surface remote from the top surface, and a first opening extending from the rear surface towards the front surface. The method can also include forming at least one second opening extending from the first opening towards the bottom surface of a respective one of the pads. The method can also include forming a conductive via, a conductive interconnect, and a contact, the conductive via in registration with and in contact with the conductive pad and extending within the second opening, the contact exposed at an exterior of the microelectronic unit, the conductive interconnect electrically connecting the conductive via with the contact and extending away from the via at least partly within the first opening. | 03-14-2013 |
20130127000 | Interposer Package For CMOS Image Sensor And Method Of Making Same - An image sensor package and method of manufacture that includes a crystalline handler with conductive elements extending therethrough, an image sensor chip disposed in a cavity of the handler, and a transparent substrate disposed over the cavity and bonded to both the handler and image sensor chip. The transparent substrate includes conductive traces that electrically connect the sensor chip's contact pads to the handler's conductive elements, so that off-chip signaling is provided by the substrate's conductive traces and the handler's conductive elements. | 05-23-2013 |
20130168791 | Quantum Efficiency Back Side Illuminated CMOS Image Sensor And Package, And Method Of Making Same - An image sensor device (and method of making same) that includes a substrate with front and back opposing surfaces, a plurality of photo detectors formed at the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the photo detectors. A cavity is formed into the back surface. A plurality of secondary cavities are formed into a bottom surface of the cavity such that each secondary cavity is disposed over one of the photo detectors. Absorption compensation material having light absorption characteristics that differ from those of the substrate is disposed in the secondary cavities. A plurality of color filters are each disposed in the cavity or in one of the secondary cavities and over one of the photo detectors. The plurality of photo detectors are configured to produce electronic signals in response to light incident through the color filters. | 07-04-2013 |
20130188267 | Multi-Layer Polymer Lens And Method Of Making Same - A multi-layered lens having a substrate with opposing first and second surfaces. The substrate is formed of a plurality of discreet polymer layers. A cavity is formed into the first surface and is defined by a non-planar cavity surface that acts as a lens surface. The cavity extends into and exposes each of the plurality of polymer layers. The compositions of the polymer layers can vary to provide optimized focal properties. Alignment marks in the form of cavities or protrusions can be formed at the first surface or the second surface, so that multiple lenses can be stacked together in an aligned manner to form a stacked lens assembly. | 07-25-2013 |
20130242155 | Back Side Illuminated Image Sensor Architecture, And Method Of Making Same - An image sensor device that includes a substrate and a plurality of color filters. The substrate includes a plurality of photo detectors (wherein a first portion of the plurality of photo detectors each has a lateral size that is smaller than that of each of a second portion of the plurality of photo detectors) and a plurality of contact pads which are electrically coupled to the photo detectors. The plurality of color filters are each disposed over one of the photo detectors. The plurality of photo detectors are configured to produce electronic signals in response to light incident through the color filters. A third portion of the plurality of photo detectors are laterally disposed between the first and second portions of the photo detectors, and each having a lateral size between those of the first and second portions of the photo detectors. | 09-19-2013 |
20130249031 | Quantum Efficiency Back Side Illuminated CMOS Image Sensor And Package, And Method Of Making Same - An image sensor device (and method of making same) that includes a substrate with front and back opposing surfaces, a plurality of photo detectors formed at the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the photo detectors. A plurality of cavities are formed into a back surface of the substrate such that each cavity is disposed over one of the photo detectors. Absorption compensation material having light absorption characteristics that differ from those of the substrate is disposed in the cavities. A plurality of color filters are each disposed over one of the photo detectors. The plurality of photo detectors are configured to produce electronic signals in response to light incident through the color filters. | 09-26-2013 |
20130273693 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 10-17-2013 |
20130300009 | Method Of Making Stamped Multi-Layer Polymer Lens - A method of forming lenses includes providing a lens handler having a plurality of cavities formed into an upper surface thereof. For each of the cavities, the method includes dispensing a first polymer material into the cavity, pressing a non-planar stamp surface onto the first polymer material wherein an upper surface of the first polymer material is conformed to the non-planar stamp surface, and applying UV light to the first polymer material to cure the first polymer material. A dispenser carrier can be used that includes a plurality of liquid polymer dispensers. A stamp carrier can be used that includes a plurality of stamps each having a non-planar stamp surface. Alternately, a stamp handler having a plurality of stamps arranged along a curved surface can be used to roll along the polymer material such that an upper surface thereof conforms to the non-planar stamp surfaces. | 11-14-2013 |
20130313680 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates. | 11-28-2013 |
20130330905 | EDGE CONNECT WAFER LEVEL STACKING - A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package. | 12-12-2013 |
20130341804 | SIMULTANEOUS WAFER BONDING AND INTERCONNECT JOINING - Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip. | 12-26-2013 |
20140004646 | Method Of Making 3D Integration Microelectronic Assembly For Integrated Circuit Devices | 01-02-2014 |
20140004647 | Method Of Forming 3D Integrated Microelectronic Assembly With Stress Reducing Interconnects | 01-02-2014 |
20140004664 | Method Of Making 3D Integration Microelectronic Assembly For Integrated Circuit Devices | 01-02-2014 |
20140027612 | Integrated Image Sensor Package With Liquid Crystal Lens - A package structure with a sensor chip having a first substrate with front and back opposing surfaces, a plurality of photo detectors and contact pads formed at the front surface and electrically coupled together, a plurality of first electrical contacts each extending from the back surface and through the first substrate to one of the contact pads, and a plurality of second electrical contacts each extending from the back surface and through the first substrate to the front surface. The liquid crystal lens includes a layer of liquid crystal material, one or more lead patterns adjacent the layer of liquid crystal material, and a plurality of third electrical contacts each extending from one of the one or more lead patterns. The sensor chip is mounted to the liquid crystal lens such that each of the third electrical contacts is electrically connected to one of the plurality of second electrical contacts. | 01-30-2014 |
20140048954 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES WITH PLURAL ACTIVE CHIPS - A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle. | 02-20-2014 |
20140065755 | Method Of Making A Low Stress Cavity Package For Back Side Illuminated Image Sensor - An image sensor package includes an image sensor chip and crystalline handler. The image sensor chip includes a substrate, and a plurality of photo detectors and contact pads at the front surface of the substrate. The crystalline handler includes opposing first and second surfaces, and a cavity formed into the first surface. A compliant dielectric material is disposed in the cavity. The image sensor front surface is attached to the crystalline substrate handler second surface. A plurality of electrical interconnects each include a hole aligned with one of the contact pads, with a first portion extending from the second surface to the cavity and a second portion extending through the compliant dielectric material, a layer of insulation material formed along a sidewall of the first portion of the hole, and conductive material extending through the first and second portions of the hole and electrically coupled to the one contact pad. | 03-06-2014 |
20140070349 | Low Profile Image Sensor Package And Method - An image sensor package, and method of making same, that includes a printed circuit board having a first substrate with an aperture extending therethrough, one or more circuit layers, and a plurality of first contact pads electrically coupled to the one or more circuit layers. A sensor chip mounted to the printed circuit board and disposed at least partially in the aperture. The sensor chip includes a second substrate, a plurality of photo detectors formed on or in the second substrate, and a plurality of second contact pads formed at the surface of the second substrate which are electrically coupled to the photo detectors. Electrical connectors each electrically connect one of the first contact pads and one of the second contact pads. A lens module is mounted to the printed circuit board and has one or more lenses disposed for focusing light onto the photo detectors. | 03-13-2014 |
20140097546 | MULTI-FUNCTION AND SHIELDED 3D INTERCONNECTS - A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element. | 04-10-2014 |
20140099754 | COMPLIANT INTERCONNECTS IN WAFERS - A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit. | 04-10-2014 |
20140131892 | CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING - An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element. | 05-15-2014 |
20140151881 | PACKAGED SEMICONDUCTOR CHIPS WITH ARRAY - A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device. | 06-05-2014 |
20140203452 | ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN - A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity. | 07-24-2014 |
20140206147 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP - A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad. | 07-24-2014 |
20140210104 | NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS - A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate. | 07-31-2014 |
20140248736 | Method Of Forming A Low Profile Image Sensor Package - An image sensor package, and method of making same, that includes a printed circuit board having a first substrate with an aperture extending therethrough, one or more circuit layers, and a plurality of first contact pads electrically coupled to the one or more circuit layers. A sensor chip mounted to the printed circuit board and disposed at least partially in the aperture. The sensor chip includes a second substrate, a plurality of photo detectors formed on or in the second substrate, and a plurality of second contact pads formed at the surface of the second substrate which are electrically coupled to the photo detectors. Electrical connectors each electrically connect one of the first contact pads and one of the second contact pads. A lens module is mounted to the printed circuit board and has one or more lenses disposed for focusing light onto the photo detectors. | 09-04-2014 |
20140264691 | Low Profile Image Sensor - A sensor package comprising a host substrate with opposing first and second surfaces, an aperture extending therethrough, circuit layers, and first contact pads. A second substrate at least partially in the aperture has opposing first and second surfaces, a plurality of photo detectors, second contact pads at the second substrate first surface and electrically coupled to the photo detectors, and trenches formed into the second substrate first surface, conductive traces extending from the second contact pads and into the trenches. A third substrate has a first surface mounted to the first surface of the second substrate. The third substrate includes a cavity formed into its first surface and positioned over the photo detectors. Electrical connectors connect the first contact pads and conductive traces. A lens module is mounted to the host substrate for focusing light through the third substrate and onto the photo detectors. | 09-18-2014 |
20140264692 | Low Profile Sensor Module And Method Of Making Same - A host substrate assembly includes a first substrate with opposing first and second surfaces, an aperture extending therethrough, circuit layers, and first contact pads electrically coupled to the circuit layers. A sensor chip includes a second substrate with opposing first and second surfaces, a plurality of photo detectors formed on or in the second substrate and configured to receive light incident on the second substrate first surface, and a plurality of second contact pads formed at the second substrate first or second surfaces and are electrically coupled to the photo detectors. A spacer is mounted to the second substrate first surface. A protective substrate is mounted to the spacer and disposed over the photo detectors. Electrically conductive conduits each extend through the spacer and are in electrical contact with one of the second contact pads. Electrical connectors electrically connect the first contact pads and the conduits. | 09-18-2014 |
20140264693 | Cover-Free Sensor Module And Method Of Making Same - A sensor package includes host substrate assembly includes a first substrate, circuit layers in the first substrate, and first contact pads electrically coupled to the circuit layers. A sensor chip includes a second substrate with opposing first and second surfaces, sensor(s) formed on or under the first surface of the second substrate, a plurality of second contact pads formed at the first surface of the second substrate and which are electrically coupled to the sensor(s), a plurality of holes each formed into the second surface of the second substrate and extends through the second substrate to one of the second contact pads, and conductive leads each extending from one of the second contact pads, through one of the plurality of holes, and along the second surface of the second substrate. A plurality of electrical connectors each electrically connect one of the first contact pads and one of the conductive leads. | 09-18-2014 |
20140273393 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape. | 09-18-2014 |
20140322856 | METHOD OF MAKING INTERPOSER PACKAGE FOR CMOS IMAGE SENSOR - An image sensor package and method of manufacture that includes a crystalline handler with conductive elements extending therethrough, an image sensor chip disposed in a cavity of the handler, and a transparent substrate disposed over the cavity and bonded to both the handler and image sensor chip. The transparent substrate includes conductive traces that electrically connect the sensor chip's contact pads to the handler's conductive elements, so that off-chip signaling is provided by the substrate's conductive traces and the handler's conductive elements. | 10-30-2014 |
20140342503 | COMPLIANT INTERCONNECTS IN WAFERS - A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit. | 11-20-2014 |
20140353789 | Sensor Package With Exposed Sensor Array And Method Of Making Same - A packaged sensor assembly and method of forming that includes a first substrate having opposing first and second surfaces and a plurality of conductive elements each extending between the first and second surfaces. A second substrate comprises opposing front and back surfaces, one or more detectors formed on or in the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the one or more detectors. A third substrate is mounted to the front surface to define a cavity between the third substrate and the front surface, wherein the third substrate includes a first opening extending from the cavity through the third substrate. The back surface is mounted to the first surface. A plurality of wires each extend between and electrically connecting one of the contact pads and one of the conductive elements. | 12-04-2014 |
20150021788 | Multi-Function and Shielded 3D Interconnects - A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element. | 01-22-2015 |
20150054001 | Integrated Camera Module And Method Of Making Same - A camera module and method of making same, includes a substrate of conductive silicon having top and bottom surfaces, a sensor device, and an LED device. The substrate includes a first cavity formed into the bottom surface of the substrate and has an upper surface, an aperture extending from the first cavity upper surface to the top surface of the substrate, and a second cavity formed into the top surface of the substrate and having a lower surface. The sensor device includes at least one photodetector, is disposed at least partially in the first cavity, and is mounted to the first cavity upper surface. The LED device includes at least one light emitting diode, is disposed at least partially in the second cavity, and is mounted to the second cavity lower surface. | 02-26-2015 |
20150079733 | THREE-DIMENSIONAL SYSTEM-IN-A-PACKAGE - A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having at least a portion having a thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements. | 03-19-2015 |
20150084148 | Low Profile Sensor Package With Cooling Feature And Method Of Making Same - A sensor device and method of making same that includes a silicon substrate with opposing first and second surfaces, a sensor formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the sensor, and a plurality of cooling channels formed as first trenches extending into the second surface but not reaching the first surface. The cooling channels instead can be formed on one or more separate substrates that are attached to the silicon substrate for cooling the silicon substrate. | 03-26-2015 |