Patent application number | Description | Published |
20140015021 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 01-16-2014 |
20140138744 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS - Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion. | 05-22-2014 |
20140168263 | CONSUMER ELECTRONICS WITH AN INVISIBLE APPEARANCE - A method, electronic device and system for displaying background images on an electronic device, wherein the electronic device includes a face that has at least one edge and a display visible in the face. The display extends to at least one edge of the face. Furthermore, a processor is coupled to the display and a photosensor is coupled to the processor. The photosensor is configured to capture background images of a background obscured behind the device when viewing the device face. The processor is configured to composite the background image with a second image. | 06-19-2014 |
20140175376 | Reduced Scale Resonant Tunneling Field Effect Transistor - An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein. | 06-26-2014 |
20140176615 | TRANSPARENT DISPLAY USING SELECTIVE LIGHT FILTERING - A transparent display device and method of forming such device. The transparent display device includes a substrate, wherein the substrate allows greater than 50% of incident light to pass through the substrate. The device also includes a plurality of pixels formed on the substrate, wherein the pixels are formed of an adjustable permittivity material wherein the adjustable permittivity material exhibits a change in permittivity upon the application of a voltage and is normally transparent. The device further includes interconnects operatively coupled to the adjustable permittivity material in each pixel, wherein the interconnects are configured to provide voltage to the adjustable permittivity material. | 06-26-2014 |
20150041847 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS - Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion. | 02-12-2015 |
20150179650 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 06-25-2015 |
20160056278 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) WITH UNDOPED DRAIN UNDERLAP WRAP-AROUND REGIONS - Tunneling field effect transistors (TFETs) with undoped drain underlap wrap-around regions are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region formed above a substrate. The homojunction active region includes a doped source region, an undoped channel region, a wrapped-around region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wrapped-around regions. | 02-25-2016 |