Patent application number | Description | Published |
20140374771 | SEMICONDUCTOR MULTI-LAYER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 μm. | 12-25-2014 |
20150069410 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, SCHOTTKY BARRIER DIODE, AND FIELD EFFECT TRANSISTOR - A semiconductor device includes: a base; an electron transit layer layered on the base; an electron-supplying layer being configured by layering a plurality of AlN layers and GaN layers alternately on the electron transit layer and having an average Al composition x; an etching sacrificial layer layered on the electron-supplying layer and made of Al | 03-12-2015 |
20150221725 | SEMICONDUCTOR MULTI-LAYER SUBSTRATE AND SEMICONDUCTOR ELEMENT - A semiconductor multi-layer substrate includes a substrate, a buffer layer formed on the substrate and made of a nitride semiconductor, an electric-field control layer formed on the buffer layer and made of a nitride semiconductor, the electric-field control layer having conductivity in the substrate's lateral direction, an electric-field relaxation layer formed on the electric-field control layer and made of a nitride semiconductor, and an active layer formed on the electric-field relaxation layer and made of an nitride semiconductor. A resistance in the substrate's lateral direction of the electric-field control layer is equal to or smaller than 10 times a resistance of the electric-field relaxation layer, and a ratio of an electric field share between the electric-field relaxation layer and the buffer layer is controlled by a ratio between a thickness of the electric-field relaxation layer and a thickness of the buffer layer. | 08-06-2015 |
Patent application number | Description | Published |
20090245508 | CONVERTER, ENCRYPTION/DECRYPTION SYSTEM, MULTI-STAGE CONVERTER, CONVERTING METHOD, MULTI-STAGE CONVERTING METHOD, PROGRAM, AND INFORMATION RECORDING MEDIUM - A converter uses a predetermined parameter a. A generating unit accepts generated inputs x | 10-01-2009 |
20100020888 | COMMUNICATION SYSTEM, COMMUNICATION METHOD AND INFORMATION RECORDING MEDIUM - In order to transmit and receive not less than a binary digital signal using a code table in which chaotic map is used and an independent component analysis, a transmitting device ( | 01-28-2010 |
20100232523 | COMMUNICATION SYSTEM, TRANSMITTING DEVICE, RECEIVING DEVICE, AND INFORMATION RECORDING MEDIUM - A communication system ( | 09-16-2010 |
20130036059 | ELECTRONIC PRICE-PROPOSING SYSTEM, ELECTRONIC PRICE-PROPOSING DEVICE, AND ELECTRONIC PRICE-PROPOSING METHOD - An electronic price-proposing server is provided with: a secret-key recording means for recording identification codes assigned individually to multiple user terminals and calculation values thereof, in association with each of the users as secret keys thereof, an encrypting means for generating encryption data with the chaotic encryption method, a price-data recording means for recording the encryption data in association with the corresponding item and user, a searching means for searching for and reading encryption data corresponding to requests from user terminals, and a transmitting means for transmitting the result thereof to the user terminals. Meanwhile, the user terminals are provided with: a decrypting means for decrypting the received encrypted data, using an identification-code value read out from an identification-code value reading means, and generating the original price data, and a displaying means for displaying the decrypted price data. | 02-07-2013 |
Patent application number | Description | Published |
20110180208 | METHOD FOR LAMINATING PREPREG, METHOD FOR PRODUCING PRINTED WIRING BOARD AND PREPREG ROLL - A method for laminating a prepreg contributing to decrease in layer thickness and having high productivity, a method for producing a printed wiring board by the method for laminating the prepreg, and a prepreg roll used for the method for laminating the prepreg are provided. The method involves: 1) preparing a prepreg roll comprising a prepreg comprising at least a core layer, a first resin layer, a second resin layer, being thicker than the first resin layer, and a supporting base film which covers the first resin layer, wherein the prepreg with the supporting base film is rolled up into a roll; 2) unreeling the prepreg with the supporting base film from the prepreg roll, peeling off the peelable film if the second resin layer is covered with the peelable film, and layering the prepreg with the supporting base film on a circuit board so that the second resin layer side of the prepreg with the supporting base film faces a circuit of the circuit board; 3) vacuum laminating the prepreg; and 4) smoothing a surface of the first resin layer contacting the supporting base film by hot press. | 07-28-2011 |
20110255258 | RESIN COMPOSITION, PREPREG, RESIN SHEET, METAL-CLAD LAMINATE, PRINTED WIRING BOARD, MULTILAYER PRINTED WIRING BOARD AND SEMICONDUCTOR DEVICE - Disclosed is a resin composition exhibiting a low thermal expansion coefficient, as well as higher heat resistance, flame resistance and insulation reliability than ever before when used in a multilayer printed wiring board that requires fine wiring work. Also disclosed are a prepreg, a resin sheet, a metal-clad laminate, a printed wiring board, a multilayer printed wiring board and a semiconductor device, all of which comprising the resin composition. The resin composition of the present invention comprises (A) an epoxy resin, (B) a cyanate resin and (C) an onium salt compound as essential components. | 10-20-2011 |
Patent application number | Description | Published |
20090081856 | SINGLE CRYSTAL SILICON WAFER FOR INSULATED GATE BIPOLAR TRANSISTORS AND PROCESS FOR PRODUCING THE SAME - A single crystal silicon wafer for use in the production of insulated gate bipolar transistors is made of single crystal silicon grown by the Czochralski method and has a gate oxide with a film thickness of from 50 to 150 nm. The wafer has an interstitial oxygen concentration of at most 7.0×10 | 03-26-2009 |
20100051945 | SILICON WAFER AND METHOD FOR PRODUCING THE SAME - A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×10 | 03-04-2010 |
20100052103 | SILICON WAFER AND METHOD FOR PRODUCING THE SAME - A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×10 | 03-04-2010 |
20100111802 | METHOD OF MANUFACTURING SILICON SINGLE CRYSTAL, SILICON SINGLE CRYSTAL INGOT, AND SILICON WAFER - By determining a control direction of a pulling-up velocity without using a position or a width of an OSF region as an index, a subsequent pulling-up velocity profile is fed back and adjusted. A silicon single crystal ingot that does not include a COP and a dislocation cluster is grown by a CZ method, a silicon wafer is sliced from the silicon single crystal ingot, reactive ion etching is performed on the silicon wafer in an as-grown state, and a grown-in defect including silicon oxide is exposed as a protrusion on an etching surface. A growing condition in subsequent growing is fed back and adjusted on the basis of an exposed protrusion generation region. As a result, feedback with respect to a nearest batch can be performed without performing heat treatment to expose a defect. | 05-06-2010 |
20100288184 | SILICON SINGLE CRYSTAL WAFER FOR IGBT AND METHOD FOR MANUFACTURING SILICON SINGLE CRYSTAL WAFER FOR IGBT - A method for manufacturing a silicon single crystal wafer for IGBT, including introducing a hydrogen atom-containing substance into an atmospheric gas at a hydrogen gas equivalent partial pressure of 40 to 400 Pa, and growing a single crystal having an interstitial oxygen concentration of 8.5×10 | 11-18-2010 |
20100290971 | SILICON WAFER AND METHOD FOR PRODUCING THE SAME - It is possible to provide a silicon wafer that as well as being free of COPs and dislocation clusters, has defects (grown-in defects including silicon oxides), which are not overt in an as-grown state, such as OSF nuclei and oxygen precipitate nuclei existing in the PV region, to be vanished or reduced, by adopting a method for producing a silicon wafer, the method comprising the steps of: growing a single crystal silicon ingot by the Czochralski method; cutting a silicon wafer out of the ingot; subjecting the wafer to an RTP at 1,250° C. or more for 10 seconds or more in an oxidizing atmosphere; and removing a grown-in defect region including silicon oxides in the vicinity of wafer surface layer after the RTP. | 11-18-2010 |
20110052923 | METHOD OF PRODUCING EPITAXIAL WAFER AS WELL AS EPITAXIAL WAFER - An epitaxial wafer is produced by a method comprising steps of growing a silicon single crystal ingot having a given oxygen concentration through Czochralski method, cutting out a wafer from the silicon single crystal ingot, subjecting the wafer to a heat treatment at a given temperature for a given time, and epitaxially growing the wafer. | 03-03-2011 |