Ueng
Chian-Her Ueng, Chaozhou Township TW
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20120025356 | SEMICONDUCTOR DEVICE PACKAGES HAVING ELECTROMAGNETIC INTERFERENCE SHIELDING AND RELATED METHODS - The semiconductor device package includes a conformal shield layer applied to the exterior surface of the encapsulant. and an internal fence or separation structure embedded in the encapsulant. The fence separates the package into various compartments. with each compartment containing at least one die. The fence thus suppresses EMI between adjacent packages. The package further includes a ground path connected to the internal fence and conformal shield. | 02-02-2012 |
Jyh-Chang Ueng, Taipei City TW
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20120263169 | METHOD FOR APPLYING INTERNET TELEPHONE SERVICE BY CONVENTIONAL TELEPHONE WITH INTERNET TELEPHONY GATEWAY - The present invention provides a method for applying internet telephone service system by conventional telephone with internet telephony gateway. By message processors receiving and sending message and processing message between conventional telephone and internet telephone service system, and by a command set built-in second message processor, the user is capable of having internet telephone service system on a conventional telephone. In practice, the user can press the keys on the conventional telephone to select an account displayed on Caller ID display module thereon and then make a call to the account; additional system information such as unanswered internet calls or remaining credits of the internet telephone service system can also be displayed thereon. | 10-18-2012 |
Jznn-Pyng Ueng, Makung TW
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20090133638 | Aquarium - An aquarium includes: a box having an accommodating space therein; a dividing board disposed in the accommodating space of the box to divide it into a cultivating layer and a nitrobacteria layer; a pump for drawing water and air, mixing them into bubbles, and sending the mixture out via a transporting pipe; a foam remover connected with the transporting pipe and having a foam outlet and a water outlet. The bubbles received from the transporting pipe are broken into smaller bubbles in the foam remover. The protein impurities in the water are expelled with the bubbles via the foam outlet. The processed water flows via the water outlet into the nitrobacteria layer to decompose the proteins. | 05-28-2009 |
Neng-Tsann Ueng, Bellevue, WA US
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20150257050 | TRAFFIC MANAGEMENT FOR HETEROGENOUS NETWORKS - This disclosure relates to cell selection of a telecommunication device based on mobility management algorithms for idle mode cell selection routines and handover routines. The mobility management algorithm can utilize the BTS class of the infrastructure equipment to help determine cell selection. The BTS class of the infrastructure equipment can be used to determine the geographic size of the coverage area that the infrastructure equipment provides. These algorithms can be used to help handle mobility management for telecommunication device. | 09-10-2015 |
20150257124 | TRAFFIC MANAGEMENT FOR HETEROGENOUS NETWORKS - This disclosure relates to cell selection of a telecommunication device based on mobility management algorithms for idle mode cell selection routines and handover routines. The mobility management algorithm can utilize the BTS class of the infrastructure equipment to help determine cell selection. The BTS class of the infrastructure equipment can be used to determine the geographic size of the coverage area that the infrastructure equipment provides. These algorithms can be used to help handle mobility management for telecommunication device. | 09-10-2015 |
Shih-Yuan Ueng, Hsinchu City TW
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20130037880 | TRENCH-GATE METAL OXIDE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer. | 02-14-2013 |
20140094013 | FABRICATING METHOD OF TRENCH-GATE METAL OXIDE SEMICONDUCTOR DEVICE - A fabricating method of a trench-gate metal oxide semiconductor device is provided. The fabricating method includes the steps of defining a first zone and a second zone in a substrate, forming at least one first trench in the second zone, forming a dielectric layer on the first zone and the second zone, filling the dielectric layer in the first trench, performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask, forming a first gate dielectric layer on a sidewall of the second trench, and filling a conducting material layer into the second trench, thereby forming a first gate electrode. | 04-03-2014 |
Su-Wen Ueng, Wilsonville, OR US
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20100322690 | PRINT MEDIA PREHEATING SYSTEM AND METHOD OF USE - A print media preheating system and method of preheating print media that includes an upper heating plate that is arranged to heat a pre-printed side of the print media with a pressure of the upper heating plate on the print media being relieved by lifting the upper heating plate away from the print media so as to reduce smudging of ink printed on the pre-printed side of the print media. | 12-23-2010 |
Yeong-Luh Ueng, Kinmen County TW
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20110161770 | LOW DENSITY PARITY CHECK CODEC AND METHOD OF THE SAME - The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced. | 06-30-2011 |
20130139031 | LOW DENSITY PARITY CHECK CODEC - The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced. | 05-30-2013 |
20140223261 | UNEQUAL BIT RELIABILITY INFORMATION STORAGE METHOD FOR COMMUNICATION AND STORAGE SYSTEMS - An unequal bit-reliability information storage method for communication and storage systems at least includes one storage unit having a first memory and a second memory; the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory. Based on the significance of each bit of the information with the use of the first or second memories of different reliability for storage, the complexity of the storage unit, the production cost and the power consumption can be reduced while maintaining the performance | 08-07-2014 |
20140281786 | LAYERED DECODING ARCHITECTURE WITH REDUCED NUMBER OF HARDWARE BUFFERS FOR LDPC CODES - A layered decoding architecture with a reduced number of hardware buffers for low-density parity-check (LDPC) decoding by storing a variable-to-check message. When a check node begins a new operation, a variable-to-check message (Q) is added to a check-to-variable message (R) obtained in previous check-node operation to obtain an updated APP value. Then, the R value for the check node in the layer being processed is deducted from the APP value to obtain a variable-to-check message (Q). This variable-to-check message is stored in the memory and inserted into the check node equation to obtain a check-to-variable message. Finally the check-to-variable message obtained in this operation is stored to the check-to-variable message shift register to complete the updating operation for the check node and the variable node for the layer being processed. Improved hardware utilization and fewer buffers, thus achieving a smaller hardware area while retaining the converge speed, is obtained. | 09-18-2014 |
Yeong-Luh Ueng, Jinning Township TW
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20110126078 | DECODER AND DECODING METHOD FOR LOW-DENSITY PARITY CHECK CODES CONSTRUCTED BASED ON REED-SOLOMON CODES - Configurable permutators in an LDPC decoder are provided. A partially-parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multi-mode function. To overcome the difficulty in efficient implementation of a high-throughput decoder, the variable nodes are partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and, hence, increase the maximum operating frequency. In addition, shuffled message-passing decoding can be adopted in decoders according to the invention to increase the convergence speed, which reduces the number of iterations required to achieve a given bit-error-rate performance. | 05-26-2011 |
Yeong-Luh Ueng, Hsin-Chu City TW
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20080285432 | Method for Generating Candidates used in Turbo Coded Orthogonal Frequency-Division Multiplexing System with Selective Mapping Technique - A method for generating candidate used in TCOFDM (turbo coded orthogonal frequency-division multiplexing) with SLM (selective mapping) technique, a user data is combined with a plurality of seeds to generate corresponding a plurality of message vectors. The method is characterized in performing tail-biting turbo encoding on the message vectors to generate corresponding turbo codewords used for generating candidates, and the seed of each message vector is different from the seeds of other message vectors. | 11-20-2008 |
20090049357 | Decoding Method for Quasi-Cyclic Low-Density Parity-Check Codes and Decoder for The Same - A decoding method for quasi-cyclic low-density parity-check (QC-LDPC) codes sequentially decodes a plurality of block codes defined by an identical parity-check matrix derived from a parity-check matrix of the QC-LDPC codes, wherein size of the identical parity-check matrix is smaller than size of the parity-check matrix. | 02-19-2009 |
Yeong-Luh Ueng, Hsinchu City TW
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20140223253 | METHOD OF EARLY TERMINATION OF CHANNEL DECODING BY RE-ENCODING - A method of early termination for channel decoding by re-encoding according to the invention at least includes a decoding unit, an encoding unit connected to the decoding unit, and a checking unit connected to the decoding unit and the encoding unit; by means of the configuration of the above units, decoded message words produced from the decoding unit are sent back to the encoding unit for re-encoding; the re-encoded words are compared to the decoded codewords by the checking unit; and if they are completely the same, then terminate the decoding action of the decoding unit. It achieves saved power consumption, simplified structure, improved decoding throughput and less hardware complexity. | 08-07-2014 |
Yeong-Luh Ueng, Hsinchu TW
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20100153819 | Decoding Method and System for Low-Density Parity Check Code - A decoding method for LDPC code includes steps of obtaining a set of parity-check matrices of a set of block codes; obtaining an identical parity-check matrix from the set of parity-check matrices; dividing the identical parity-check matrix into an odd identical parity-check matrix and an even identical parity-check matrix, wherein the odd identical parity-check matrix being composed of odd rows of the identical parity-check matrix, and the even identical parity-check matrix being composed of even rows of the identical parity-check matrix; and decoding the set of block codes basing on the odd identical parity-check matrix and the even identical parity-check matrix. | 06-17-2010 |
20130173981 | NON-BINARY QC-LDPC CODE DECODING DEVICE AND ASSOCIATED METHOD - A non-binary quasi-cyclic (QC) low-density parity-check (LDPC) code decoding device comprises a first barrel-shifter, a routing network and a second barrel-shifter. The first barrel-shifter uses a constraint h′v′+h″v″=hv to shift q−1 elements of an input by j | 07-04-2013 |