Ueguri, JP

Toru Ueguri, Tokyo JP

Patent application number	Description	Published
20090152697	SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.	06-18-2009
20100258945	SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a method for manufacturing a semiconductor device involving the step of bonding a metallic ribbon to a pad of a semiconductor chip, breakage of the metallic ribbon is to be prevented while ensuring the bonding strength even when the metallic ribbon becomes thin with reduction in size of the semiconductor chip. In bonding an Al ribbon to a pad of a semiconductor chip by bringing a pressure bonding surface of a wedge tool into pressure contact with the Al ribbon while applying ultrasonic vibration to the ribbon positioned over the pad, recesses	10-14-2010
20110073921	SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.	03-31-2011

Toru Ueguri, Kanagawa JP

Patent application number	Description	Published
20140084436	SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained.	03-27-2014
20140087520	METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).	03-27-2014

Toru Ueguri, Kawasaki-Shi JP

Patent application number	Description	Published
20150214209	Method of Manufacturing Semiconductor Device - To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).	07-30-2015

Toshiaki Ueguri, Kawasaki-Shi JP

Patent application number	Description	Published
20100265340	CONTROL APPARATUS, CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A control apparatus for controlling an image capture apparatus includes a communication unit and a control unit. The communication unit transmits a first command to the image capture apparatus if a predetermined area in a captured image received from the image capture apparatus and a pointer operated by an operation unit are overlapped. The communication unit transmits a second command to the image capture apparatus if a button of the operation unit is clicked in a state that the predetermined area and the pointer are overlapped.	10-21-2010
20130176444	CONTROL APPARATUS, CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A control apparatus for controlling an image capture apparatus includes a communication unit and a control unit. The communication unit transmits a first command to the image capture apparatus if a predetermined area in a captured image received from the image capture apparatus and a pointer operated by an operation unit are overlapped. The communication unit transmits a second command to the image capture apparatus if a button of the operation unit is clicked in a state that the predetermined area and the pointer are overlapped.	07-11-2013

Toyohiro Ueguri, Gunma JP

Patent application number	Description	Published
20090020158	Method for manufacturing solar cell and solar cell, and method for manufacturing semiconductor device - The present invention is a method for manufacturing a solar cell by forming a p-n junction in a semiconductor substrate having a first conductivity type, wherein, at least: a first coating material containing a dopant and an agent for preventing a dopant from scattering, and a second coating material containing a dopant, are coated on the semiconductor substrate having the first conductivity type so that the second coating material may be brought into contact with at least the first coating material; and, a first diffusion layer formed by coating the first coating material, and a second diffusion layer formed by coating the second coating material the second diffusion layer having a conductivity is lower than that of the first diffusion layer are simultaneously formed by a diffusion heat treatment; a solar cell manufactured by the method; and a method for manufacturing a semiconductor device. It is therefore possible to provide the method for manufacturing the solar cell, which can manufacture the solar cell whose photoelectric conversion efficiency is improved at low cost and with a simple and easy method by suppressing surface recombination in a portion other than an electrode of a light-receiving surface and recombination within an emitter while obtaining ohmic contact; the solar cell manufactured by the method; and the method for manufacturing the semiconductor device.	01-22-2009
20110045624	PHOSPHORUS PASTE FOR DIFFUSION AND PROCESS FOR PRODUCING SOLAR BATTERY UTILIZING THE PHOSPHORUS PASTE - Disclosed is a phosphorus paste for diffusion that is used in continuous printing of a phosphorus paste for diffusion on a substrate by screen printing. The phosphorus paste for diffusion does not undergo a significant influence of ambient humidity on viscosity and has no possibility of thickening even after a large number of times of continuous printing. The phosphorus paste for diffusion is coated on a substrate by screen printing for diffusion layer formation on the substrate. The phosphorus paste for diffusion includes a doping agent containing phosphorus as a dopant for the diffusion layer, a thixotropic agent containing an organic binder and a solid matter, and an organic solvent. The doping agent is an organic phosphorus compound.	02-24-2011

Toyohiro Ueguri, Annaka JP

Patent application number	Description	Published
20090194151	Semiconductor substrate, method for forming electrode, and method for fabricating solar cell - The present invention is directed to a semiconductor substrate having at least an electrode formed thereon, in which the electrode has a multilayer structure including two or more layers, of the multilayer structure, at least a first electrode layer directly bonded to the semiconductor substrate contains at least silver and a glass frit, and contains, as an additive, at least one of oxides of Ti, Bi, Zr, V, Nb, Ta, Cr, Mo, W, Mn, Fe, Co, Ni, Si, Al, Ge, Sn, Pb, and Zn, and, of an electrode layer formed on the first electrode layer, at least an uppermost electrode layer to be bonded to a wire contains at least silver and a glass frit and does not contain the additive. This makes it possible to form, on a semiconductor substrate, an electrode adhered to the semiconductor substrate with sufficient adhesive strength and adhered to a wire via solder with sufficient adhesive strength by lowering both contact resistance and interconnect resistance.	08-06-2009
20090243111	SEMICONDUCTOR SUBSTRATE, ELECTRODE FORMING METHOD, AND SOLAR CELL FABRICATING METHOD - The present invention is directed to a semiconductor substrate having an electrode formed thereon, the electrode including at least silver and glass frit, the electrode including: a multi-layered structure constituted of a first electrode layer joined directly to the semiconductor substrate, and an upper electrode layer formed of at least one layer and disposed on the first electrode layer; wherein the upper electrode layer is formed by firing a conductive paste having a total silver content of 75 wt % or more and 95 wt % or less, the content of silver particles having an average particle diameter of 4 μm or greater and 8 μm or smaller with respect to the total silver content in the upper electrode layer being higher than that in the first electrode layer. As a consequence, it is possible to form the electrode, which has the high aspect ratio and hardly suffers an inconvenience such as a break, on the semiconductor substrate by a simple method.	10-01-2009
20120289044	SEMICONDUCTOR SUBSTRATE, ELECTRODE FORMING METHOD, AND SOLAR CELL FABRICATING METHOD - A semiconductor substrate having an electrode formed thereon, the electrode including at least silver and glass frit, the electrode including: a multi-layered structure with a first electrode layer joined directly to the semiconductor substrate, and an upper electrode layer formed of at least one layer and disposed on the first electrode layer. The upper electrode layer is formed by firing a conductive paste having a total silver content of 75 wt % or more and 95 wt % or less, the content of silver particles having an average particle diameter of 4 μm or greater and 8 μm or smaller with respect to the total silver content in the upper electrode layer being higher than that in the first electrode layer.	11-15-2012