Patent application number | Description | Published |
20090195327 | TRANSMITTING RADIO FREQUENCY SIGNAL IN SEMICONDUCTOR STRUCTURE - A semiconductor device for transmitting a radio frequency signal along a signal line includes a signal line that extends along a principal axis. On one side of the signal line is a first dielectric, and on the opposite side of the signal line is a second dielectric. First and second ground lines are proximate to the first and second dielectrics, respectively, and the ground lines are approximately parallel to the signal line. The device has a transverse cross-section that varies along the principal axis. | 08-06-2009 |
20110260819 | CONTINUOUSLY TUNABLE INDUCTOR WITH VARIABLE RESISTORS - An integrated tunable inductor includes a primary inductor having a plurality of inductor turns, at least one closed loop eddy current coil proximate the primary inductor, and at least one variable resistor integrated in series with the eddy current coil. | 10-27-2011 |
20120092121 | BALANCED TRANSFORMER STRUCTURE - A multi-chip electronic device includes a first winding having a first port (P+) and a second port (P−). The first winding is formed in a metal layer of a first chip. The device further includes a second winding having a third (S+) and a fourth port (S−). The second winding is formed in a metal layer of a second chip. A center tap of the second winding is connected to a reference potential. | 04-19-2012 |
20120122395 | THROUGH CHIP COUPLING FOR SIGNAL TRANSPORT - Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit. | 05-17-2012 |
20130106532 | BAND-PASS FILTER USING LC RESONATORS | 05-02-2013 |
20130181534 | THROUGH-CHIP INTERFACE (TCI) STRUCTURE FOR WIRELESS CHIP-TO-CHIP COMMUNICATION - A transformer for RF and other frequency through-chip-interface (TCI) applications includes multiple chips in wireless electronic communication with one another in three-dimensional integrated circuit, 3DIC, technology. Each of the chips includes an inductor coil and a matching network that matches the impedance of the inductor coil. The matching network is electrically coupled between the inductor coil and further components and circuits formed on the chip. | 07-18-2013 |
20130207230 | ON-CHIP FERRITE BEAD INDUCTOR - A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes. | 08-15-2013 |
20130241634 | RF CALIBRATION THROUGH-CHIP INDUCTIVE COUPLING - An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils. | 09-19-2013 |
20130271223 | AMPLIFIER WITH FLOATING WELL - A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit. | 10-17-2013 |
20130328623 | LOW POWER ACTIVE FILTER - Some embodiments relate to a band-pass filter arranged in a ladder-like structure. The band-pass filter includes respective inductor-capacitor (LC) resonators arranged on respective rungs of the ladder-like structure. Respective matching circuits are arranged on a leg of the ladder-like structure between neighboring rungs. | 12-12-2013 |
20140036396 | INTEGRATED PASSIVE DEVICE FILTER WITH FULLY ON-CHIP ESD PROTECTION - The present disclosure relates to an on-chip electrostatic discharge (ESD) protection circuit that may be reused for a variety of integrated circuit (IC) applications. Both inductor-capacitor (LC) parallel resonator and shunt inductor (connected to ground) are used as ESD protection circuits and also as a part of an impedance matching network for a given IC application. The ESD LC resonator can be designed with a variety of band pass filter (BPF) topologies. On-chip ESD protection circuit allows for co-optimization ESD and BPF performance simultaneously, a fully on-chip ESD solution for integrated passive device (IPD) processes, eliminates a need for active ESD device protection, additional processes to support off-chip ESD protection, reduces power consumption, and creates a reusable BPF topology. | 02-06-2014 |
20140132333 | SWITCH CIRCUIT AND METHOD OF OPERATING THE SWITCH CIRCUIT - A method of electrically coupling a first node and a second node of a switch cell includes biasing the second node and a bias node of the switch cell at a direct current (DC) voltage level of a second voltage level greater than a first voltage level. A first switch unit coupled between the first node and the second node is tuned on by a first control signal having a third voltage level. The third voltage level being greater than the first voltage level, and a difference between the third voltage level and the first voltage level is about twice a difference between the second voltage level and the first voltage level. Also, a second switch unit coupled between the second node and the bias node is turned off by a second control signal having the first voltage level. | 05-15-2014 |
20140183660 | POWER CELL AND POWER CELL CIRCUIT FOR A POWER AMPLIFIER - A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin. | 07-03-2014 |
20140184275 | POWER CELL, POWER CELL CIRCUIT FOR A POWER AMPLIFIER AND A METHOD OF MAKING AND USING A POWER CELL - A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer. | 07-03-2014 |
20140266419 | VOLTAGE CONTROLLER FOR RADIO-FREQUENCY SWITCH - One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example. | 09-18-2014 |
20140266512 | CMOS BAND-PASS FILTER - A band-pass filter is provided that is configured to output a signal with a frequency within a desired frequency range and to attenuate signals with frequencies outside the desired frequency range. The band-pass filter comprises a CMOS resonator that comprises a resonator cavity and a reflector. The band-pass filter also comprises an impedance convertor that is configured to inhibit at least some insertion losses on the band-pass filter. The band-pass filter also comprises a variable capacitor that is connected between the CMOS resonator and the impedance convertor. The desired frequency range of the band-pass filter can be tuned by adjusting the capacitance of the variable capacitor. | 09-18-2014 |
20140374881 | CONCENTRIC CAPACITOR STRUCTURE - A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates. | 12-25-2014 |
20150014786 | HIGH PERFORMANCE POWER CELL FOR RF POWER AMPLIFIER - A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the depletion or Schottky MOSFET. The source node of the enhancement MOSFET and source node of the depletion or Schottky MOSFET are connected together to form the power cell. | 01-15-2015 |
20150015336 | CMOS CASCODE POWER CELLS - A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well. | 01-15-2015 |
20150084158 | THREE DIMENSIONAL CIRCUIT INCLUDING SHIELDED INDUCTOR AND METHOD OF FORMING SAME - The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier. | 03-26-2015 |