| Patent application number | Description | Published |
|---|
| 20140097889 | INTERFACE CIRCUIT - An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage. | 04-10-2014 |
| 20140176227 | DATA CONTROL CIRCUIT - A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit. | 06-26-2014 |
| 20140198021 | DISPLAY DRIVING APPARATUS - A display driving apparatus, including an image processor, a timing controller, and a plurality of source drivers, is provided. The image processor determines whether an image frame corresponding to a frame data is a static image and outputs the frame data and a determination result. The timing controller receives the frame data from the image processor and outputs the frame data. The source drivers receive the frame data from the timing controller and drive a display panel according to the frame data. Each of the source drivers includes a memory module configured to store the frame data corresponding to the static image. When the source drivers drive the display panel according to the frame data corresponding to the static image, the image processor stops outputting the frame data to the timing controller, and the timing controller stops outputting the frame data to the source drivers. | 07-17-2014 |
| 20150109027 | DATA CONTROL CIRCUIT - A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit. | 04-23-2015 |
| 20160043860 | CLOCK AND DATA RECOVERY APPARATUS - A clock and data recovery apparatus which includes a voltage controlled delay line (VCDL), a phase detector (PD) and a control voltage generating circuit is provided. The VCDL generates a plurality of clock signals with different phases according to a reference clock signal and a control voltage. The PD detects the phase relationship between a first input signal and a second input signal, and produces a detection result. A data signal or one of the clock signals is used as the first input signal, and one or more of the clock signals is/are used as the second input signal. The control voltage generating circuit generates the control voltage to the VCDL according to the detection result of the PD. | 02-11-2016 |
| Patent application number | Description | Published |
|---|
| 20130095644 | PLANARIZATION PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION - The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature. | 04-18-2013 |
| 20130164930 | GATE HEIGHT LOSS IMPROVEMENT FOR A TRANSISTOR - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures. | 06-27-2013 |
| 20140370696 | MECHANISMS FOR FORMING OXIDE LAYER OVER EXPOSED POLYSILICON DURING A CHEMICAL MECHANICAL POLISHING (CMP) PROCESS - Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation. | 12-18-2014 |
| 20150187594 | Composite Structure for Gate Level Inter-Layer Dielectric - A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process. | 07-02-2015 |
| Patent application number | Description | Published |
|---|
| 20080231329 | DIFFERENTIAL SIGNAL OUTPUT CIRCUIT FOR TIMING CONTROLLER OF DISPLAY DEVICE - A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for receiving a differential signal and outputting a current to a load circuit according to polarity of the differential signal. The pre-charging circuit is coupled to a first output end and a second output end of the conversion circuit or is coupled to a first power driving end and a power second driving end of the conversion circuit. The pre-charging circuit is used for pre-charging the load according to a control signal. The timing generator is used for generating the differential signal and a control signal according to display data. | 09-25-2008 |
| 20090116564 | LOW VOLTAGE DIFFERENTIAL SIGNALING TRANSMITTER AND TRANSMITTING METHOD - A low voltage differential signaling (LVDS) transmitter receives a data signal, a data invert signal and a plurality of logic signals. The LVDS transmitter includes a first-stage differential signaling transmitting circuit and a second-stage differential signaling transmitting circuit. The first-stage differential signaling transmitting circuit receives the data signal and the data invert signal and has a first output terminal and a second output terminal. The second-stage differential signaling transmitting circuit is controlled by the logic signals, and has a third output terminal and a fourth output terminal respectively connected to the first output terminal and the second output terminal, so as to generate a needed pre-emphasis signal. When no pre-emphasis signal needs to be generated, the second-stage differential signaling transmitting circuit is controlled to be in disabled state. | 05-07-2009 |
| 20090160495 | LOW POWER DIFFERENTIAL SIGNALING TRANSMITTER - A low power differential signaling transmitter includes a switchable current source apparatus and a differential signaling generator coupled to the switchable current source apparatus. The switchable current source apparatus receives a first input voltage and a second input voltage, and generates a plurality of reference currents according to the first input voltage and the second input voltage. The differential signaling generator includes a plurality of first transistors, a plurality of second transistors, a first output voltage terminal and a second output voltage terminal. The on or off states of the first transistors and the second transistors are controlled by the reference currents. The first output voltage terminal outputs a first output voltage, and the second output voltage terminal outputs a second output voltage. The first output voltage and the second output voltage are determined according to the on or off states of the first and second transistors. | 06-25-2009 |
| 20090262840 | Synchronization Signal Extraction Device and Related Method - A synchronization signal extraction device includes a signal reception terminal for receiving a composite video signal, a threshold voltage adjuster coupled to the signal reception terminal for adjusting a threshold voltage to a ratio of a first characteristic level and a second characteristic level of the composite video signal according to the first characteristic level and the second characteristic level, a slicer coupled to the signal reception terminal and the threshold voltage adjuster for slicing the composite video signal to extract a synchronization signal in the composite video signal, and a signal output terminal coupled to the slicer for outputting the extracted synchronization signal. | 10-22-2009 |
| 20090303217 | TRANSMISSION INTERFACE FOR REDUCING POWER CONSUMPTION AND ELECTROMAGNETIC INTERFERENCE AND METHOD THEREOF - The exemplary examples of the present invention provide a transmission interface and method thereof for reducing power consumption and electromagnetic interference. The transmission interface is used in the Liquid Crystal Display (LCD), and the LCD has x source drivers. The i | 12-10-2009 |
| 20100289467 | POWER SUPPLY CIRCUIT AND METHOD THEREOF - In a normal mode, the power supply is fed back in a close loop, but in a power saving mode, the power supply is fed back in an open loop. When it is detected that the power supply is continuously fed back in the open loop and in a substantially zero output status, the power supply circuit enters a power down status. If the back-stage circuit needs power supply again, then the feedback is switched to the close loop and the power supply circuit enters the normal mode. | 11-18-2010 |
| 20110032977 | Dual-Port Input Equalizer - A dual-port input equalizer includes a control unit for generating a first control signal and a second control signal according to a selection signal, a first equalizer for receiving a first and second differential voltage for equalization according to the first control signal and the second control signal, which the first equalizer includes a first transistor, a second transistor, an passive loading portion, and a first zero-point generation circuit, a second equalizer for receiving a third and fourth differential voltage for equalization according to the first control signal and the second control signal, which the second equalizer includes a third transistor and a fourth transistor, which the drain of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the passive loading portion, and the source of the first transistor, the second transistor, third transistor, and the fourth transistor coupled to the first zero-point generation circuit. | 02-10-2011 |
| 20120068714 | Short Detection Circuit, Light-Emitting Diode Chip, Light-Emitting Diode Device and Short Detection Method - A short detection circuit includes a voltage divider circuit, for generating, according to a bottom voltage of one or more light-emitting diode strings, a divided voltage less than the bottom voltage. Additionally, the short detection circuit includes a voltage clamp circuit, coupled to the voltage divider circuit, for clamping the divided voltage, and a comparator, coupled to the voltage divider circuit, for comparing the divided voltage and a reference voltage, to decide whether a short circuit occurs in the one or more light-emitting diode strings according to a result of the comparison. | 03-22-2012 |
| 20120075356 | INTEGRATED BACKLIGHT DRIVING CHIP AND LED BACKLIGHT DEVICE - An integrated backlight driving chip for driving a light-emitting diode backlight module includes a scaler circuit and a backlight driving circuit. The scaler circuit includes a digital control unit for generating a digital control signal, and a variable reference voltage generation unit for generating a reference voltage. The backlight driving circuit is coupled to the digital control unit, the variable reference voltage generation unit, and the LED backlight module, for generating a backlight driving signal according to the digital control signal and the reference voltage so as to drive the LED backlight module. | 03-29-2012 |
| 20120086359 | Light-Emitting Diode Driving Device, Light-Emitting Diode Device, and Method for Driving the Same - A light-emitting diode driving device includes a light-emitting diode driving chip, for driving the one or more light-emitting diode strings according to a feedback voltage associated with the one or more light-emitting diode strings, and a voltage limiter, having a terminal coupled to the light-emitting diode driving chip and another terminal coupleable to the one or more light-emitting diode strings, for generating the feedback voltage for provision to the light-emitting diode driving chip according to a bottom voltage of the one or more light-emitting diode strings, and limiting the feedback voltage not to exceed a preset level. | 04-12-2012 |
| 20120268022 | IMAGE PROCESSING CIRCUIT AND LIGHT ILLUMINATION MODULE - An image processing circuit and a light illumination module are provided. The light illumination module has an integrated circuit and a plurality of light emitting diode (LED) strings connected in parallel. The integrated circuit could be the image processing circuit. Each of the LED strings has a plurality of LEDs connected in series. | 10-25-2012 |
| 20140354623 | Light-Emitting Diode Driving Device, Light-Emitting Diode Device, and Method for Driving the Same - A light-emitting diode driving device includes a light-emitting diode driving chip, for driving the one or more light-emitting diode strings according to a feedback voltage associated with the one or more light-emitting diode strings, and a voltage limiter, having a terminal coupled to the light-emitting diode driving chip and another terminal coupleable to the one or more light-emitting diode strings, for generating the feedback voltage for provision to the light-emitting diode driving chip according to a bottom voltage of the one or more light-emitting diode strings, and limiting the feedback voltage not to exceed a preset level; wherein the voltage limiter starts limiting the feedback voltage to substantially the preset level when the bottom voltage rises to the preset level. | 12-04-2014 |
| Patent application number | Description | Published |
|---|
| 20120210038 | EXTERNAL BRIDGE SYSTEM - An external bridge system includes a host interface, a first device interface and a second device interface, which uses a communication protocol different from that of the first device interface. A bridge controller translates signals compliant with the communication protocol of a host to or from signals compliant with the communication protocol of the first or second device. | 08-16-2012 |
| 20130179749 | METHOD AND SYSTEM OF DYNAMIC DATA STORAGE FOR ERROR CORRECTION IN A MEMORY DEVICE - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, the received data is encoded and error correction code (ECC) is generated. The encoded data is stored in the memory device that includes a plurality of pages each having a plurality of data partitions. More corrected errors a marked page has, a smaller portion with a space of at least one datum of each of the corresponding data partitions associated with the marked page is allocated to store the encoded data, while a size of the ECC is fixed, thereby increasing capability of correcting errors in the marked page. | 07-11-2013 |
| 20140344502 | Method of Accessing On-Chip Read Only Memory and Computer System Thereof - A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address. | 11-20-2014 |
| Patent application number | Description | Published |
|---|
| 20090283953 | AUTOMATIC SHEET FEEDER WITH RETRACTABLE SHEET SUPPORTING STRUCTURE - An automatic sheet feeder includes a body, a sheet-feeding mechanism and a sheet supporting structure. The body has a sheet passageway which has an input end and an output end. The sheet-feeding mechanism disposed in the body feeds a sheet from the input end into the sheet passageway and then discharges the sheet out of the output end. The sheet supporting structure, disposed at one of the input end and the output end and pivotally connected to the body, supports the sheet to be fed into the input end or the sheet to be discharged from the output end. The sheet supporting structure is rotatable relatively to the body and can be thus spread out or retracted relatively to the body. | 11-19-2009 |
| 20090283959 | AUTOMATIC IMAGE PROCESSING APPARATUS AND SHEET FEEDING DEVICE THEREOF - An automatic image processing apparatus includes a sheet feeding device and an image processing device. The sheet feeding device supports a plurality of sheets and feeds the sheets one by one. The image processing device receives the sheets coming from the sheet feeding device one by one, and feeds and processes the sheets one by one. The sheet feeding device is removably connected to the image processing device, and receives mechanical power from the image processing device and thus feeds the sheets one by one. The sheet feeding device for the automatic image processing apparatus is also disclosed. | 11-19-2009 |
| 20100244363 | FEEDING MECHANISM AND IMAGE PROCESSING APPARATUS USING THE SAME - The present invention provides a feeding mechanism and an image processing apparatus using the same. The feeding mechanism includes an upper casing, a lower casing disposed opposite the upper casing, a sheet tray, a main feeding roller, a sheet-separation member and a first auxiliary roller. The upper casing and the lower casing form a transporting path. The sheet tray for loading a sheet is coupled with the lower casing. The main feeding roller for feeding the sheet in a feeding direction is disposed in the lower casing. The sheet-separation member, disposed at a downstream position of the main feeding roller with respect to the feeding direction, separates the sheet from another sheet. The first auxiliary roller is disposed in the lower casing and on a lateral side of the main feeding roller for feeding the sheet in the feeding direction. | 09-30-2010 |
| 20100276867 | SHEET-FEEDING MECHANISM AND IMAGE PROCESSING DEVICE USING THE SAME - The present invention provides a sheet-feeding mechanism and an image processing device using the same. The sheet-feeding mechanism comprises: an upper housing and a lower housing disposed opposite the upper housing, an input tray, a main roller, a separating device, a first auxiliary roller and a first pressing unit. | 11-04-2010 |
| 20120081764 | SHEET-FED SCANNER WITH LINKING MEMBER - A sheet-fed scanner includes a housing, a scan assembly carrier, a scan assembly and a bent linking member. The scan assembly carrier is movably disposed in the housing. The scan assembly mounted in the scan assembly carrier scans a side of an original sheet in a main scan direction. The bent linking member disposed between the housing and the scan assembly carrier includes a first section and a second section. The first section extends transversally in relation to the main scan direction and interconnecting two opposed ends of the scan assembly carrier. The second section, connected with the first section, forms an angle with the first section. As one of two opposed ends of the scan assembly carrier is pushed towards the housing in a direction, the bent linking member urges the other end to move in the same direction. | 04-05-2012 |
| 20120307324 | COMPACT MULTI-FUNCTIONAL SCANNING APPARATUS WITH RETRACTABLE FLATBED SCANNER - A compact multi-functional scanning apparatus includes a sheet-fed scanner, a casing and a flatbed scanner. The casing is attached to the sheet-fed scanner and has a recess. The flatbed scanner is movable between a retracted position within the recess and a deployed position outside the recess. In the deployed position the flatbed scanner is enabled to perform a flatbed-scanning task. An open end of the recess is located on a lateral side of the casing, and the flatbed scanner is movable into and out of the recess through the open end. | 12-06-2012 |
| 20150304513 | PERIPHERAL WITH INDEPENDENT FLATBED AND SHEET-FED SCANNING DEVICES - A peripheral comprises a flatbed scanning device, a sheet-fed scanning device and a multi-stage input tray. The flatbed scanning device comprises a rotatable upper cover covering a first document, on which a flatbed scan is performed. The sheet-fed scanning device abuts upon the upper cover and performs a sheet-fed scan on a second document. The multi-stage input tray comprises a first tray and a second tray. The first tray is disposed on the upper cover and has a supporting surface for supporting the second document. The second tray, pivotally connected to the first tray, assists in supporting the second document in a deployed mode, and forms an inverse-V-shaped structure with the supporting surface in a retracted mode. | 10-22-2015 |
| Patent application number | Description | Published |
|---|
| 20090161426 | MEMORY PROGRAMMING METHOD AND DATA ACCESS METHOD - A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed. | 06-25-2009 |
| 20090161440 | INTEGRATED CIRCUITS AND DISCHARGE CIRCUITS - An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period. | 06-25-2009 |
| 20090167094 | VOLTAGE ADJUSTING CIRCUITS AND VOLTAGE ADJUSTING METHODS - A voltage adjusting circuit is provided. The voltage adjusting circuit for adjusting the output voltages supplied by voltage sources includes a test control device, a multiplexer, a comparator, and a built in self test (BIST) device. The test control device selects one of the voltage sources as a testing voltage source, and outputs a selecting command for selecting the testing voltage source and a target voltage corresponding to the testing voltage source. The multiplexer is coupled to the voltage sources, receives an enablement signal, and outputs a voltage supplied by the testing voltage source as a testing voltage according to the enablement signal. The comparator compares the voltage levels of the testing voltage and the target voltage, and outputs a comparison result. The BIST device receives the selecting command, outputs the enablement signal for enabling the testing voltage source according to the selecting command, and adjusts the voltage supplied by the testing voltage source to a predetermined voltage according to the comparison result. | 07-02-2009 |
| 20090177851 | MEMORY DEVICE AND DATA READING METHOD - A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data includes a plurality of flag bits. The determining circuit generates a determination bit according to the flag bits. The data reading circuit obtains information corresponding to the main data according to the determination bit. | 07-09-2009 |
| 20090273391 | FLASH MEMORIES AND REGULATED VOLTAGE GENERATORS THEREOF - A flash memory and a regulated voltage generator thereof. The regulated voltage generator includes a charge pump having an output terminal outputting a first voltage, a control circuit coupled to the output terminal of the charge pump and having first and second output terminals outputting a second voltage and a charge pump control signal, respectively, and a Field Effect Transistor (FET) in diode mode. The FET is coupled between the output terminal of the charge pump and the first output terminal of the control circuit. The charge pump adjusts the first voltage according to the charge pump control signal. | 11-05-2009 |
| Patent application number | Description | Published |
|---|
| 20130271626 | METHOD OF REDUCING COLUMN FIXED PATTERN NOISE - A method of reducing column fixed pattern noise including calibrating a readout circuit, wherein the readout circuit is electrically connected to at least one programmable gain amplifier and an analog-to-digital converter. Calibrating the readout circuit includes electrically disconnecting the readout circuit from a pixel output and electrically connecting a pixel reset input of the readout circuit to a pixel output signal input of the readout circuit. Calibrating the readout circuit further includes comparing a measured output of the readout circuit to a predetermined value and storing the comparison result in a non-transitory computer readable medium. The method further includes operating the readout circuit, the operating the readout circuit includes receiving a pixel sample signal and outputting a calibrated output based on an operating output and the stored comparison result. | 10-17-2013 |
| 20140217263 | IMAGE SENSOR CONFIGURED TO REDUCE BLOOMING DURING IDLE PERIOD - Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image. | 08-07-2014 |
| 20140347535 | APPARATUS WITH CALIBRATED READOUT CIRCUIT - An apparatus comprises a readout circuit configured to be disconnected from a pixel output, and to connect a pixel reset signal received by the readout circuit to a pixel output signal received by the readout circuit. The apparatus also comprises at least one programmable gain amplifier coupled with the readout circuit. The apparatus further comprises an analog-to-digital converter coupled with the programmable gain amplifier. The readout circuit is configured to be calibrated based on a comparison of a measured output of the readout circuit to a predetermined value, the predetermined value being equal to (2 | 11-27-2014 |
| 20150116506 | NOISE SIMULATION FLOW FOR LOW NOISE CMOS IMAGE SENSOR DESIGN - A method for noise simulation of a CMOS image sensor comprises performing a frequency domain noise simulation for a readout circuit of the CMOS image sensor using a computer, wherein the readout circuit includes a correlated double sampling (CDS) circuit, wherein the frequency domain noise simulation includes a CDS transfer function to refer a noise introduced by the CDS circuit back to an input node of the readout circuit. The method further comprises calculating noise at the input node of the readout circuit based on the referred back noises caused by one or more components in the readout circuit and estimating noise of the CMOS imaging sensor by comparing the calculated noise at the input node of the readout circuit to an original input signal to the readout circuit of the CMOS imaging sensor. | 04-30-2015 |
| 20150215556 | READOUT DEVICE WITH READOUT CIRCUIT - A readout device comprises a readout circuit having a first switch configured to receive a pixel reset signal, a second switch configured to receive a pixel output signal, and a third switch configured to connect the first switch to the second switch. A first capacitor is connected to the first switch, a second capacitor is connected the second switch, a fourth switch is connected to the first capacitor, and a fifth switch is connected to the second capacitor. The fifth switch is connected to the fourth switch. The readout circuit also comprises a sixth switch connected to the first capacitor and a seventh switch connected to the second capacitor. The sixth switch is configured to provide a first output of the readout circuit, and the seventh is configured to provide a second output of the readout circuit. | 07-30-2015 |
| Patent application number | Description | Published |
|---|
| 20130009071 | SPECIMEN BOX FOR ELECTRON MICROSCOPE - The present invention relates to a specimen box for an electron microscope, comprising a first substrate, a second substrate, one or more photoelectric elements, and a metal adhesion layer. The first substrate has a first surface, a second surface, a first concave, and one or more first through holes, wherein the first through holes penetrate through the first substrate. The second substrate has a third surface, a forth surface, and a second concave. The photoelectric element is disposed between the first substrate and the second substrate. In addition, the metal adhesion layer is disposed between the first substrate and the second substrate to form a space for a specimen contained therein. Besides, the present specimen box further comprises one or more plugs. When the plugs are assembled into the first through holes to seal the specimen box, the in-situ observation can be accomplished by using the electron microscope. | 01-10-2013 |
| 20130009072 | SPECIMEN BOX FOR ELECTRON MICROSCOPE - The present invention relates to a specimen box for an electron microscope, which comprises a first substrate, a second substrate, and a metal adhesion layer. The first substrate has a first surface, a second surface, a first concave, and one or more first through holes, wherein the first through hole penetrates through the first substrate. The second substrate has a third surface, a forth surface, and a second concave. Besides, the metal adhesion layer is disposed between the first substrate and the second substrate to form a space for a specimen placed therein. In addition, the specimen box of the present invention further comprises one or more plugs. When the plug is assembled into the first through hole to seal the specimen box, the in-situ observation can be accomplished by using an electron microscope. | 01-10-2013 |
| 20130037940 | METHOD FOR INHIBITING GROWTH OF INTERMETALLIC COMPOUNDS - The present invention relates to a method for inhibiting growth of intermetallic compounds, comprising the steps of: (i) preparing a substrate element including a substrate on which at least one layer of metal pad is deposited, wherein at least one thin layer of solder is deposited onto the layer of metal pad, and then carry out reflowing process; and (ii) further depositing a bump of solder with an appropriate thickness on the substrate element, characterized in that a thin intermetallic compound is formed by the reaction of the thin solder layer and the metal in the metal pad after appropriate heat treatment of the thin solder layer. In the present invention, the formation of a thin intermetallic compound is able to slow the growth of the intermetallic compound and to prevent the transformation of the intermetallic compounds. | 02-14-2013 |
| 20130122326 | Electrodeposited Nano-Twins Copper Layer and Method of Fabricating the Same - An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process. | 05-16-2013 |
| 20150064496 | SINGLE CRYSTAL COPPER, MANUFACTURING METHOD THEREOF AND SUBSTRATE COMPRISING THE SAME - The present invention relates to a single crystal copper having [100] orientation and a volume of 0.1˜4.0×10 | 03-05-2015 |
| Patent application number | Description | Published |
|---|
| 20100251068 | STORAGE CONTROLLER WITH ENCODING/DECODING CIRCUIT PROGRAMMABLE TO SUPPORT DIFFERENT ECC REQUIREMENTS AND RELATED METHOD THEREOF - One exemplary storage controller of controlling data access of a storage device includes an encoding circuit and a control circuit. The encoding circuit is programmable to support a plurality of different finite fields, and implemented for generating encoded data according to an adjustable finite field setting. The control circuit is implemented for controlling the adjustable finite field setting of the encoding circuit and recording data into the storage device according to the encoded data. Another exemplary storage controller of controlling data access of a storage device includes a decoding circuit and a control circuit. The decoding circuit is programmable to support a plurality of different finite fields, and implemented for generating decoded data according to an adjustable finite field setting. The control circuit is implemented for reading data from the storage device to obtain readout data and controlling the adjustable finite field setting of the decoding circuit. | 09-30-2010 |
| 20100332734 | FLASH MEMORY DEVICES AND METHODS FOR CONTROLLING A FLASH MEMORY DEVICE - A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array. | 12-30-2010 |
| 20100332887 | STORAGE CONTROL DEVICE HAVING CONTROLLER OPERATED ACCORDING TO DETECTION SIGNAL DERIVED FROM MONITORING POWER SIGNAL AND RELATED METHOD THEREOF - One exemplary storage control device for a storage medium includes a controller and a voltage detector, where the controller controls data access of the storage medium, and the voltage detector monitors a power signal and asserts a detection signal to notify the controller when anomaly of the power signal is detected. Another exemplary storage control device for a storage medium includes a voltage detector and a controller, where the voltage detector monitors a power signal to generate a detection signal, and the controller controls data access of the storage medium. In addition, the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and enters a second operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range. | 12-30-2010 |
| 20100332922 | METHOD FOR MANAGING DEVICE AND SOLID STATE DISK DRIVE UTILIZING THE SAME - A solid state disk drive is provided. The solid state disk drive includes a multiple level cell (MLC) memory device and a controller. The MLC memory device includes memory blocks each comprising memory cells capable of storing more than a single bit of data per cell. The controller transforms at least one memory block into a single level cell (SLC)-like memory block, and accesses the memory block in an SLC manner. | 12-30-2010 |
| 20120207191 | WIRELESS COMMUNICATION DEVICE - A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package. | 08-16-2012 |
| 20140189415 | MEDIA PERIPHERAL INTERFACE, ELECTRONIC DEVICE WITH MEDIA PERIPHERAL INTERFACE, AND COMMUNICATION METHOD BETWEEN PROCESSOR AND PERIPHERAL DEVICE - A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured. | 07-03-2014 |
| 20150140939 | WIRELESS COMMUNICATION DEVICE - A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package. | 05-21-2015 |
| 20150155905 | WIRELESS COMMUNICATION DEVICE - A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the RF unit and the first memory are packaged in a single semiconductor device. | 06-04-2015 |
| 20150277401 | LOW-POWER MECHANISM FOR WEARABLE CONTROLLER AND ASSOCIATED CONTROL METHOD - A low-power wearable controller and associated control method are provided. The wearable controller includes: a processing unit; a memory unit; a peripheral interface unit including a plurality of peripheral interfaces; and a control module, coupled to the processing unit, the memory unit and the peripheral interface unit, wherein the control module is enabled when the wearable controller is operated in a first operation mode, and the control module is disabled when the wearable controller is operated in a second operation mode. | 10-01-2015 |
| 20160055031 | Dual-System Architecture With Fast Recover And Switching Of Operating System - Examples of a dual-system architecture capable of fast switching between the operating systems are provided. A first operating system may perform one or more operations associated with an apparatus as an active operating system of the apparatus. The active operating system may be switched from the first operating system to a second operating system for the second operating system to perform a task responsive to a determination that the second operating system is required to perform the task. | 02-25-2016 |
| 20160134324 | WIRELESS COMMUNICATION DEVICE - A wireless communication device including an integrated processing circuit, a first memory and a testing circuit is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit. The testing circuit is coupled to the first memory, and is capable of testing the first memory for determining if the first memory is an effective memory. The RF unit and the first memory are placed in a single module. | 05-12-2016 |
| Patent application number | Description | Published |
|---|
| 20130194861 | SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION - A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal. | 08-01-2013 |
| 20140063918 | CONTROL CIRCUIT OF SRAM AND OPERATING METHOD THEREOF - A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needed boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage. | 03-06-2014 |
| 20150162077 | STATIC MEMORY CELL - A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data. | 06-11-2015 |
| 20160027500 | CIRCUIT FOR MITIGATING WRITE DISTURBANCE OF DUAL-PORT SRAM - A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates. | 01-28-2016 |
| Patent application number | Description | Published |
|---|
| 20110026742 | METHOD OF FABRICATING INTEGRATED SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF - A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process. | 02-03-2011 |
| 20130037914 | NOVEL STRUCTURE OF NPN-BJT FOR IMPROVING PUNCH THROUGH BETWEEN COLLECTOR AND EMITTER - A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode. | 02-14-2013 |
| 20140111890 | BI-DIRECTIONAL BIPOLAR JUNCTION TRANSISTOR FOR HIGH VOLTAGE ELECTROSTATIC DISCHARGE PROTECTION - A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates. | 04-24-2014 |
| 20140111892 | BI-DIRECTIONAL BIPOLAR JUNCTION TRANSISTOR FOR HIGH VOLTAGE ELECTROSTATIC DISCHARGE PROTECTION - A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided. | 04-24-2014 |
| 20150044808 | METHOD OF FABRICATING INTEGRATED SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF - A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process. | 02-12-2015 |
| Patent application number | Description | Published |
|---|
| 20080252365 | APPARATUS AND METHOD FOR TUNING CENTER FREQUENCY OF A FILTER - A method for tuning a filter is provided. The method includes: enabling a VCO circuit, wherein at least a portion of the VCO circuit is selected from the filter; generating an oscillation signal by the VCO circuit according to a driving signal; comparing the oscillation signal with a reference signal and generating a comparison result; and adjusting the driving signal according to the comparison result. | 10-16-2008 |
| 20090237283 | METHOD AND APPARATUS FOR DIGITAL TO ANALOG CONVERSION - A Delta-Sigma DAC and a digital to analog conversion method are provided. A FIR filter receives a shaped digital signal to generate a first current on a first output node, and a second current on a second output node. A current inverter is coupled to the second output node, outputting a reversed current having opposite polarity and identical magnitude of the second current. A current to voltage converter is coupled to the first output node and the output of current inverter, generating an analog signal according to the first and reversed currents. A first current source compensates DC offset for the first current, and a second current source compensates DC offset for the second current. The first and second current sources are implemented by NMOS. | 09-24-2009 |
| 20090289614 | REFERENCE BUFFER CIRCUIT - A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages. | 11-26-2009 |
| 20100117827 | METHOD FOR CURRENT REDUCTION FOR AN ANALOG CIRCUIT IN A DATA READ-OUT SYSTEM - The invention provides a method for current reduction for an analog circuit in a data read-out system. First, a performance indicator, indicating a performance of the data read-out system is generated. The performance indicator is then compared with a performance threshold level to generate a switch signal. A level of a current source biasing the analog circuit is then adjusted according to the switch signal. | 05-13-2010 |
| 20100156688 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTER - A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein all switches included in the OP-amp input switch block are implemented utilizing PMOS transistors only, and the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp. | 06-24-2010 |
| 20100194614 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTER FOR High SPEED AND LOW SUPPLY VOLTAGE - A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp. | 08-05-2010 |
| Patent application number | Description | Published |
|---|
| 20120030549 | DATA TRANSMISSION DETECTING DEVICE, DATA TRANSMISSION DETECTING METHOD AND ELECTRONIC DEVICE THEREOF - A data transmission detecting device including a detecting module and a detection value calculating module is provided. The detecting module has a plurality of receiving terminals and receives a first data and a second data during a first period. The detecting module calculates a total detection value according to the first data and the second data, and performs an error check comparison by comparing the total detection value with an error check code. When the detecting module again receives the first data during a second period, the detection value calculating module transmits an auxiliary detection value to the detecting module, so that the detecting module calculates a corresponding total detection value according to the auxiliary detection value, and performs the error check comparison by comparing the total detection value with the error check code. The first period and the second period are two successive periods adjacent to each other. | 02-02-2012 |
| 20120287140 | Display Interface Circuit - A display interface circuit includes a physical layer circuit for receiving and modulating an original data signal and an original clock signal, a frame buffer for storing and outputting the data signal according to the clock signal and a command signal, a display serial interface for transmitting the data signal and the clock signal through packetization, a configuration register for generating the command signal according to an asynchronous clock signal and the data signal, and an asynchronous delay circuit for adjusting a clock latency that the clock signal takes to be sent to the configuration register to generate the asynchronous clock signal. | 11-15-2012 |
| 20140136741 | Bus Detection and Control Method and Bus Detection and Control Device and Mobile Industry Processor Interface System Thereof - A bus detection and control method for a mobile industry processor interface system is disclosed, wherein a host is coupled to a slave with a mobile industry processor interface bus. The bus detection and control method includes steps of detecting statuses of the mobile industry processor interface bus and the host, to output a control signal; and outputting one of a predefined signal corresponding to an initial state and a transmission signal outputted to the mobile industry processor interface bus by the host as a reception signal of the slave according to the control signal. | 05-15-2014 |
| 20140204068 | DISPLAY DRIVING APPARATUS AND DISPLAY DRIVING METHOD THEREOF - A display driving apparatus including a signal transmission interface, a timing control circuit and an image detection circuit is provided. The signal transmission interface is configured to receive video image data and output the video image data. The timing control circuit is configured to receive the video image data and drive a display panel based on the video image data. The image detection circuit determines whether the video image data is a static image and determines whether the display driving apparatus operates in a power-saving mode based on the determination result. Under the power-saving mode, the signal transmission interface masks a part of the video image data, so as not: to output the masked video image data to the timing control circuit. Furthermore, a display driving method adapted for the foregoing display driving apparatus is also provided. | 07-24-2014 |
| 20140211888 | MIPI SIGNAL RECEIVING APPARATUS AND METHOD - A signal receiving apparatus and method adapted for receiving a MIPI signal are disclosed. The signal receiving apparatus includes a signal receiver, a selector, a decoding apparatus and a byte boundary searcher. The signal receiver receives a clock signal, and obtains an input data stream according to the clock signal. The selector outputs the input data stream to a first or second output terminal according to a decoding error signal. The byte boundary searcher operates a boundary searching operation on the input data stream for generating a byte tuning information, wherein, the signal receiver adjusts the clock according to the byte tuning information for adjusting the input data stream. | 07-31-2014 |
| 20140372834 | Serial Interface Packet Information Detection and Control Method and Receiver Thereof - A serial interface packet information detection and control method for a Mobile Industry Processor Interface is disclosed. The serial interface packet information detection and control method includes receiving and decoding a packet; generating a control signal according to packet information of a header of the packet; and disabling a function register according to the control signal. | 12-18-2014 |
| Patent application number | Description | Published |
|---|
| 20100006997 | Chip-Stacked Package Structure with Leadframe Having Multi-Piece Bus Bar - The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces. | 01-14-2010 |
| 20100264527 | Stacked Chip Package Structure with Leadframe Having Bus Bar - The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad. | 10-21-2010 |
| 20100264530 | Stacked Chip Package Structure with Leadframe Having Bus Bar - The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad. | 10-21-2010 |
| 20100314729 | Stacked Chip Package Structure with Leadframe Having Inner Leads with Transfer Pad - The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offest chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer. | 12-16-2010 |
