Patent application number | Description | Published |
20130201648 | STACKED SUBSTRATE STRUCTURE - The instant disclosure provides a self-sealed stacked structure which includes a substrate unit, a first frame, a conductive unit and a blocker unit. The substrate unit includes a first and a second substrate, and a first frame sandwiched there-between. The conductive unit includes a plurality of first conductors and second conductors electrically connecting the first substrate, the first frame and the second substrate. The first and the second conductors are in electrical connection. A blocker unit including at least two first and at least two second blockers are surroundingly arranged around the plurality of first and second conductors, respectively. The first substrate and the first frame are connected in a sealed manner through the first blockers combined by the solder, where the first frame and the second substrate are connected in a sealed manner through the second blockers combined by the solder. | 08-08-2013 |
20140126159 | ELECTRONIC DEVICE, SYSTEM PACKAGE MODULE AND METHOD OF MANUFACTURING SYSTEM PACKAGE MODULE - A system in package (SiP) module includes a first circuit board assembly, a second circuit board assembly and a plurality of metallic pillars. The first circuit board assembly has a first top surface, a first bottom surface and a plurality of pads mounted on the first bottom surface. The second circuit board assembly has a second top surface, a second bottom surface and a plurality of second pads mounted on the second top surface. The metallic pillars are disposed between the first bottom surface and the second top surface. The metallic pillars electrically connect the first pad and the second pad. | 05-08-2014 |
20140198459 | STACKED PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF - A stacked package device includes a substrate, at least one electronic component and a molding unit. The molding unit includes a first insulation layer, a second insulation layer, and a first shielding layer. The electronic component is disposed on the substrate. The first insulation layer is disposed on the substrate and covers the electronic component. The first insulation layer has a plurality of holes, and is disposed on the first insulation layer. The second insulation layer is disposed on the first shielding layer. The first insulation layer is connected to the second insulation layer through the holes. | 07-17-2014 |
20150035201 | METHOD OF MANUFACTURING ELECTRONIC PACKAGE MODULE - A method of manufacturing electronic package module is provided. The method provides selective molding by attaching tapes on the circuit substrate on which electric components are mounted thereon, forming molding compound to cover the circuit substrate, and removing tapes along with the molding compound thereon. | 02-05-2015 |
20150036297 | ELECTRONIC MODULE AND METHOD OF MAKING THE SAME - A method of manufacturing electronic module is provided. The method can perform selective partial molding by forming the tapes in a predetermined area on the circuit substrate, setting electronic components out the predetermined area on the circuit substrate, forming the molding member encapsulating the whole circuit substrate and removing the tapes along of the molding member thereon. Following, forming an EMI shielding layer on the molding member and setting optoelectronics in the predetermined area on the circuit substrate could protect the electronic components from electromagnetic disturbance and avoid the optoelectronics being encapsulated. | 02-05-2015 |
Patent application number | Description | Published |
20140027908 | Integrated Circuit Interconnects and Methods of Making Same - A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween. | 01-30-2014 |
20140065816 | DIELECTRIC FORMATION - Among other things, one or more techniques for forming a low k dielectric around a metal line during an integrated circuit (IC) fabrication process are provided. In an embodiment, a metal line is formed prior to forming a surrounding low k dielectric layer around the metal line. In an embodiment, the metal line is formed by filling a trench space in a skeleton layer with metal. In this embodiment, the skeleton layer is removed to form a dielectric space in a different location than the trench space. The dielectric space is then filled with a low k dielectric material to form a surrounding low k dielectric layer around the metal line. In this manner, damage to the surrounding low k dielectric layer, that would otherwise occur if the surrounding low k dielectric layer was etched, for example, is mitigated. | 03-06-2014 |
20140131312 | Lithography Process Using Directed Self Assembly - A method includes forming a patterned hard mask layer, with a trench formed in the patterned hard mask layer. A Bulk Co-Polymer (BCP) coating is dispensed in the trench, wherein the BCP coating includes Poly-Styrele (PS) and Poly Methyl Metha Crylate (PMMA). An annealing is performed on the BCP coating to form a plurality of PS strips and a plurality of PMMA strips allocated in an alternating layout. The PMMA strips are selectively etched, with the PS strips left in the trench. | 05-15-2014 |
20140138801 | SEMICONDUCTOR PATTERNING - One or more techniques or systems for forming a pattern during semiconductor fabrication are provided herein. In some embodiments, a photo resist (PR) region is patterned and a spacer region is formed above or surrounding at least a portion of the patterned PR region. Additionally, at least some of the spacer region and the patterned PR region are removed to form one or more spacers. Additionally, a block co-polymer (BCP) is filled between the spacers. In some embodiments, the BCP comprises a first polymer and a second polymer. In some embodiments, the second polymer is removed, thus forming a pattern comprising the first polymer and the spacers. In this manner, a method for forming a pattern during semiconductor fabrication is provided, such that a width of the spacer or the first polymer is controlled. | 05-22-2014 |
20140252628 | INTERCONNECT STRUCTURE AND METHODS OF MAKING SAME - A method for forming a semiconductor interconnect structure comprises forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. The opening is filled and the dielectric layer is covered with a metal layer having a first etch rate. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is annealed to change the first etch rate into a second etch rate, the second etch rate being lower than the first etch rate. A copper-containing layer is formed over the annealed metal layer and the dielectric layer. The copper-containing layer has an etch rate greater than the second etch rate of the annealed metal layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the top of the annealed metal layer and does not etch thereunder. | 09-11-2014 |
20150155184 | SEMICONDUCTOR PATTERNING - One or more techniques or systems for forming a pattern during semiconductor fabrication are provided herein. In some embodiments, a photo resist (PR) region is patterned and a spacer region is formed above or surrounding at least a portion of the patterned PR region. Additionally, at least some of the spacer region and the patterned PR region are removed to form one or more spacers. Additionally, a block co-polymer (BCP) is filled between the spacers. In some embodiments, the BCP comprises a first polymer and a second polymer. In some embodiments, the second polymer is removed, thus forming a pattern comprising the first polymer and the spacers. In this manner, a method for forming a pattern during semiconductor fabrication is provided, such that a width of the spacer or the first polymer is controlled. | 06-04-2015 |
20150255389 | Integrated Circuit Interconnects and Methods of Making Same - A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween. | 09-10-2015 |
20150340283 | INTERCONNECT STRUCTURE AND METHODS OF MAKING SAME - A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy. | 11-26-2015 |