Patent application number | Description | Published |
20120207191 | WIRELESS COMMUNICATION DEVICE - A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package. | 08-16-2012 |
20130058174 | CONTROLLER AND ACCESS METHOD FOR DDR PSRAM AND OPERATING METHOD THEREOF - A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal. | 03-07-2013 |
20130058175 | DDR PSRAM AND DATA WRITING AND READING METHODS THEREOF - A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. | 03-07-2013 |
20140030374 | LEVER-TYPE MOLD EJECTION MECHANISM OF INJECTION MOLDING MACHINE - A lever-type mold ejection mechanism is arranged on a platen of a mold in the injection molding machine. The lever-type ejection mechanism includes a base body arranged on the platen; an actuating cylinder having a motion shaft; a link rod having a first end and a second end opposite to each other, wherein the first end is pivotally disposed on the base body through a first pivot axis, and the second end is pivotally disposed on an end of the motion shaft of the actuating cylinder through a second pivot axis, and the link rod has a movable ejector pin at its bottom surface adjacent to the first end; and a ejector rod resisting between the ejector pin and the mold. The actuating cylinder is operated to push the mold through the link rod in a lever manner so as to obtain enough pushing force. | 01-30-2014 |
20140043925 | DDR PSRAM AND DATA WRITING AND READING METHODS THEREOF - A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. The DDR PSRAM also includes a data transmitter and a data strobe generating unit. The data transmitter obtains data stored in the address of the memory and provides a double data rate data to the controller according to the obtained data, and the data strobe generating unit a data strobe signal to the controller and toggling the data strobe signal in response to the double data rate data. | 02-13-2014 |
20140189415 | MEDIA PERIPHERAL INTERFACE, ELECTRONIC DEVICE WITH MEDIA PERIPHERAL INTERFACE, AND COMMUNICATION METHOD BETWEEN PROCESSOR AND PERIPHERAL DEVICE - A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured. | 07-03-2014 |
20150140939 | WIRELESS COMMUNICATION DEVICE - A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package. | 05-21-2015 |