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| 20130256416 | BARCODE RECOGNION METHOD AND COMPUTER PRODUCT THEREOF - A barcode recognition method and a computer program product thereof are provided. In the barcode recognition method, at first, a foreground extraction step is performed to obtain a binary image of a barcode image. Thereafter, an alignment step is performed to calculate a center coordinate, corner coordinates, a shift vector, and a rotation angle of the target barcode in accordance with the barcode image, the binary image, the shift vector, and the rotation angle. Thereafter, positions of data space patterns, boundary patterns, and an alignment type of the target barcode are determined in accordance with the center coordinate, the corner coordinates, the shift vector, and the rotation angle of the target barcode. Then, values of the target barcode are determined in accordance with the positions of the data space patterns, the boundary patterns, and the alignment type of the target barcode. | 10-03-2013 |
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| 20110117710 | METHOD OF FABRICATING EFUSE, RESISTOR AND TRANSISTOR - A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess. | 05-19-2011 |
| 20120286390 | ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME - An electrical fuse structure includes a top fuse, a bottom fuse and a via conductive layer positioned between the top fuse and the bottom fuse for providing electric connection. The top fuse includes a top fuse length and the top fuse length is equal to or larger than a predetermined value. The bottom fuse includes a bottom fuse length larger than the top fuse length. | 11-15-2012 |
| 20130043972 | ELECTRICAL FUSE STRUCTURE - An electrical fuse structure includes a top conductive pattern having a top fuse and a top fuse extension portion, a bottom conductive pattern having a bottom fuse and a bottom fuse extension portion corresponding to the top fuse extension portion, and a via conductive layer positioned between the top fuse extension portion and the bottom fuse extension portion for electrically connecting the top fuse extension portion and the bottom fuse extension portion. | 02-21-2013 |
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| 20130135763 | PHOTOSENSITIVE RESIN COMPOSITION AND APPLICATION OF THE SAME - A photosensitive resin composition includes (A) an alkali-soluble resin, (B) a polysiloxane, (C) an ethylenically unsaturated compound, (D) a photo-initiator, (E) a black pigment, and (F) a solvent. The alkali-soluble resin includes an unsaturated-group-containing resin obtained by subjecting a mixture containing (i) an epoxy compound having at least two epoxy groups and (ii) a compound having at least one carboxyl group and at least one ethylenically unsaturated group to polymerization. A weight ratio of the unsaturated-group-containing resin to the polysiloxane ranges from 0.1 to 3.0. Application of the photosensitive resin composition is also disclosed. | 05-30-2013 |
| 20140293400 | PHOTOSENSITIVE RESIN COMPOSITION AND USES THEREOF - The invention relates to a photosensitive resin composition; especially relates to a photosensitive resin composition that has good heat-yellowing resistance, surface roughness resistance, developability and brightness. The invention also provides a white matrix, a color filter and a reflective display element. | 10-02-2014 |
| 20150115210 | PHOTOSENSITIVE RESIN COMPOSITION AND USES THEREOF - The invention relates to a photosensitive resin composition for a black matrix, a color filter formed by the black matrix, and a liquid crystal display device. The photosensitive resin composition comprises an alkali-soluble resin (A), a compound containing an ethylenically unsaturated group (B), a photoinitiator (C), a solvent (D), a black pigment (E), and a specific compound (F). The photosensitive resin composition for the black matrix has the advantage of good linearity of pattern with high finesse. | 04-30-2015 |
| 20150253464 | PHOTOSENSITIVE RESIN COMPOSITION AND USES THEREOF - The invention relates to a photosensitive resin composition for a black matrix, a color filter formed by the black matrix, and a liquid crystal display element. The photosensitive resin composition comprises an alkali-soluble resin (A), a compound (B) containing an ethylenically unsaturated group, a photoinitiator (C), a solvent (D), a black pigment (E), a compound (F) represented by Formula (a) and an epoxy resin (G) containing a fluorene skeleton represented by Formula (b). The photosensitive resin composition for the black matrix has the advantage of reducing film shrinkage and reducing roughness. | 09-10-2015 |
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| 20130049168 | RESISTOR AND MANUFACTURING METHOD THEREOF - A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor. | 02-28-2013 |
| 20130241002 | RESISTOR AND MANUFACTURING METHOD THEREOF - A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench. | 09-19-2013 |
| 20130270650 | RESISTOR AND MANUFACTURING METHOD THEREOF - A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously. | 10-17-2013 |
| 20130277754 | Semiconductor Integrated Structure - The present invention provides a resistor structure including a substrate, an ILD layer, a transistor and a resistor. The substrate includes a resistor region and an active region. The ILD layer is disposed directly on the substrate. The transistor is disposed in the active region in the ILD layer wherein the transistor includes a metal gate. The resistor is disposed in the resistor region above the ILD layer, wherein the resistor directly contacts the ILD layer. | 10-24-2013 |
| 20130307084 | RESISTOR INTEGRATED WITH TRANSISTOR HAVING METAL GATE - A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench. | 11-21-2013 |
| 20140242770 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed. | 08-28-2014 |
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| 20120187282 | IMAGE SENSOR WITH ANTI-REFLECTION LAYER AND METHOD OF MANUFACTURING THE SAME - An image sensor the image sensor comprising an absorption layer disposed on a silicon substrate, the absorption layer having at least one of SiGe or Ge, and an antireflection layer disposed directly thereon. | 07-26-2012 |
| 20120205769 | BACK SIDE ILLUMINATED IMAGE SENSOR WITH REDUCED SIDEWALL-INDUCED LEAKAGE - Provided is an image sensor device. The image sensor device includes having a front side, a back side, and a sidewall connecting the front and back sides. The image sensor device includes a plurality of radiation-sensing regions disposed in the substrate. Each of the radiation-sensing regions is operable to sense radiation projected toward the radiation-sensing region through the back side. The image sensor device includes an interconnect structure that is coupled to the front side of the substrate. The interconnect structure includes a plurality of interconnect layers and extends beyond the sidewall of the substrate. The image sensor device includes a bonding pad that is spaced apart from the sidewall of the substrate. The bonding pad is electrically coupled to one of the interconnect layers of the interconnect structure. | 08-16-2012 |
| 20130037890 | MULTIPLE GATE DIELECTRIC STRUCTURES AND METHODS OF FORMING THE SAME - The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness. | 02-14-2013 |
| 20130320420 | CMOS Image Sensors and Methods for Forming the Same - A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region. | 12-05-2013 |
| 20130341692 | Novel [N] Profile in Si-Ox Interface for CMOS Image Sensor Performance Improvement - A semiconductor device including first and second isolation regions supported by a substrate, a first array well supported by the first isolation region, the first array well having a first field implant layer embedded therein, the first field implant layer surrounding a first shallow trench isolation region, a second array well supported by the second isolation region, the second array well supporting a doped region and a drain and having a second field implant layer embedded therein, the second field implant layer surrounding a second shallow trench isolation region, a stack of photodiodes disposed in the substrate between the first and second isolation regions, and a gate oxide formed over an uppermost photodiode of the stack of the photodiodes, the gate oxide and a silicon of the uppermost photodiode forming an interface, a nitrogen concentration at the interface offset from a peak nitrogen concentration. | 12-26-2013 |
| 20140248734 | CMOS Image Sensors and Methods for Forming the Same - A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions. | 09-04-2014 |
| 20150028403 | Semiconductor Switching Device Separated by Device Isolation - A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure. | 01-29-2015 |
| 20150041945 | PICKUP DEVICE STRUCTURE WITHIN A DEVICE ISOLATION REGION - A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region. | 02-12-2015 |
| 20150255400 | Method for Forming Alignment Marks and Structure of Same - A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks. | 09-10-2015 |
| 20150263214 | CMOS Image Sensors and Methods for Forming the Same - A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions. | 09-17-2015 |
| 20160027836 | BACK SIDE ILLUMINATED IMAGE SENSOR HAVING ISOLATED BONDING PADS - Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate. | 01-28-2016 |
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| 20120160308 | PHOTOVOLTAIC CELL MODULE - A photovoltaic cell module includes a substrate, a first photovoltaic cell and a second photovoltaic cell. The substrate has first and second surfaces. The first photovoltaic cell includes a first electrode layer on the first surface, a first active layer covering the first electrode, and a second electrode covering the first active layer, and the first active layer absorbs the light having a first wavelength range. The second photovoltaic cell is serially connected with the first photovoltaic cell and includes a third electrode layer on the second surface, a second active layer covering the third electrode, and a fourth electrode covering the second active layer, and the second active layer absorbs the light having a second wavelength range. A surface of the second electrode layer of the first photovoltaic cell serves as a light incident surface and a surface of the second photovoltaic cell serves as a light reflective surface. | 06-28-2012 |
| 20120167964 | STACKED PHOTOVOLTAIC CELL MODULE - A stacked photovoltaic cell module including a substrate, a first electrode layer on the substrate, a first carrier transport layer on the first electrode layer, a first light absorption layer on the first carrier transport layer, a second electrode layer on the first light absorption layer, a first output unit electrically connected to the first electrode layer and the second electrode layer, a second carrier transport layer on the second electrode layer, a second light absorption layer on the second carrier transport layer, a third electrode layer on the second light absorption layer, and a second output unit electrically connected to the second electrode layer and the third electrode layer. The second carrier transport layer and the second light absorption layer satisfy Φ | 07-05-2012 |
| 20120167965 | STACKED PHOTOVOLTAIC CELL MODULE - A stacked photovoltaic cell module includes, sequentially stacked, a substrate, a first electrode layer, a first carrier transport layer, a first light absorption layer, a connecting layer with a reflectivity of 10-60%, a second carrier transport layer, a second light absorption layer, and a second electrode layer. The second carrier transport layer has a first refraction index n1 and a first thickness D1, and the second light absorption layer has a second refraction index n2 and a second thickness D2, and the second carrier transport layer and the second light absorption layer satisfy Φ | 07-05-2012 |
| 20120167972 | ORGANIC PHOTOVOLTAIC CELL - An organic photovoltaic cell is provided, which includes an organic active layer, a light-transmissive electrode, a reflective electrode, and an optical film. The light-transmissive electrode and the reflective electrode are respectively disposed at two opposite sides of the organic active layer. The optical film and the organic active layer are respectively disposed at two opposite sides of the light-transmissive electrode. The optical film has an inner surface and an outer surface opposite to the inner surface. The transmittance of the optical film is higher than 90% when light enters the optical film from the outer surface. The reflectivity of the inner surface is higher than 10% when the light enters the optical film from the inner surface. The haze of the optical film is higher than 90%. | 07-05-2012 |
| 20120240988 | PHOTOVOLTAIC CELL MODULE - A photovoltaic cell module includes a substrate, a first photovoltaic cell and a second photovoltaic cell. The substrate has a light conversion layer thereon, and the light conversion layer converts light having wavelength ranges from 300 nm to 500 nm to light having wavelength ranges from 500 nm to 700 nm. The first photovoltaic cell is disposed on a surface of the substrate and the second photovoltaic cell is disposed on another surface of the substrate. | 09-27-2012 |
| 20130050147 | TOUCH SENSING DEVICE - A touch sensing device includes a substrate, first and second bottom electrodes that are electrically insulated, an active layer, and first and second top electrodes. The substrate has a touch sensing region where the first bottom electrode is located and a non-touch sensing region where the second bottom electrode is located. The active layer on the substrate extends from the touch sensing region to the non-touch sensing region. The first top electrode is on the active layer and above the first bottom electrode. The second top electrode is on the active layer and above the second bottom electrode. A first portion of the active layer in the touch sensing region, the first top electrode, and the first bottom electrode constitute an optical touch sensing unit. A second portion of the active layer in the non-touch sensing region, the second top electrode, and the second bottom electrode constitute a solar cell. | 02-28-2013 |
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| 20090135863 | PROGRAMMABLE LASER DEVICE AND METHOD FOR CONTROLLING THE SAME - A programmable laser trigger device and the method for controlling the same are disclosed. The programmable laser trigger device comprises: an external signal module and a command executing module. The external signal module is capable of interfacing the inputs and outputs of waveform command and signals. The command executing module further comprises: a waveform command memory, for storing the waveform command; a waveform command decoder; a waveform generator; and a buffer memory, acting as a waveform trigger parameter buffer between the waveform command decoder and the waveform generator; wherein the waveform command decoder accesses the waveform command stored in the memory for pre-decoding an executing code while generating a sequence of waveform trigger parameters to be stored in the buffer memory, which provides the waveform generator with the sequence of waveform trigger parameters to be transformed into a pulse-width modulation (PWM) pulse train. With the aforesaid device and method, not only unequal pulse outputs can be generated with good flexibility for matching the needs of various manufacturing processes, but also through the instructions to an external feedback signal from the waveform command, the laser pulses outputted therefrom can be modulated in real time in response to the external feedback signal. | 05-28-2009 |
| 20120125901 | APPARATUS AND SYSTEM FOR IMPROVING DEPTH OF FOCUS - The present invention provides an apparatus and a system for improving depth of focus (DOF), wherein an optical lens for optical processing is actuated to vibrate whereby the DOF of the optical processing is increased due to the variation of focal point. In the embodiment of the present invention, an actuator is coupled to the optical lens for providing vibration energy wherein the optical lens is actuated by the vibration energy so as to vibrate on an optical axis thereof so as to increase the DOF during the optical processing, thereby improving the quality and efficiency of optical processing. | 05-24-2012 |
| 20140333931 | VISUAL ERROR CALIBRATION METHOD - A visual error calibration method configured to calibrate visual positioning errors of a laser processing apparatus is provided. The method includes: providing an alignment mark having at least one alignment point; locating a preset point of the alignment mark at a first preset position of a working area, and locating a preset image point at a preset position of the visible area; locating the alignment point at one of the second preset positions in the working area; adjusting parameters of a scanning module to locate an alignment image point at the preset position; relatively moving the alignment image point to positions of the visible area in sequence; recording the positions of the alignment image point in the visible area, the positions of the alignment point in the working area and the parameters of the scanning module, so as to produce an alignment table. | 11-13-2014 |
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| 20100052074 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region. | 03-04-2010 |
| 20100059833 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region. | 03-11-2010 |
| 20110018072 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A metal gate transistor is disclosed. The metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate. The metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer. | 01-27-2011 |
| 20120064679 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region. | 03-15-2012 |
| 20120142157 | Method of fabricating a semiconductor structure - The method of fabricating a semiconductor structure according to the present invention includes planarizing an inter-layer dielectric layer and further a hard mask to remove a portion of hard mask in a thickness direction. The remaining hard mask has a thickness less than the original thickness of the hard mask. The remaining hard mask and the dummy gate are removed to form a recess. After a gate material is filled into the recess, a gate with a relatively accurate height can be obtained. | 06-07-2012 |
| 20120244669 | Method of Manufacturing Semiconductor Device Having Metal Gates - The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench. | 09-27-2012 |
| 20120256276 | Metal Gate and Fabricating Method Thereof - A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O | 10-11-2012 |
| 20140339652 | SEMICONDUCTOR DEVICE WITH OXYGEN-CONTAINING METAL GATES - A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer. | 11-20-2014 |
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| 20130047049 | BUILT-IN SELF-TEST FOR INTERPOSER - A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit. | 02-21-2013 |
| 20130106459 | 3D-IC INTERPOSER TESTING STRUCTURE AND METHOD OF TESTING THE STRUCTURE | 05-02-2013 |
| 20130127441 | APPARATUS AND METHOD FOR ON-CHIP SAMPLING OF DYNAMIC IR VOLTAGE DROP - Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time. | 05-23-2013 |
| 20140049281 | Diagnosis Framework to Shorten Yield Learning Cycles of Advanced Processes - The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA). | 02-20-2014 |
| 20140272712 | E-Beam Lithography with Alignment Gating - The present disclosure provides one embodiment of a reflective electron-beam (e-beam) lithography system. The reflective e-beam lithography system includes an e-beam source to generate an e-beam; a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable to reflect the e-beam; a substrate stage designed to secure a substrate and being operable to move the substrate; an e-beam lens module configured to project the e-beam from the DPG to the substrate; and an alignment gate configured between the e-beam source and the DPG, wherein the alignment gate is operable to modulate an intensity of the e-beam. | 09-18-2014 |
| 20150153407 | Contactless Signal Testing - A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within an electron beam, converting an electrical current created by the e-beam to a voltage with a number of diodes connected to a positive voltage supply, extracting a digital test signal from the voltage signal with a digital inverter, and passing the test signal to digital circuitry within the integrated circuit. | 06-04-2015 |
| 20150187666 | INTEGRATED CIRCUIT COMPRISING BUFFER CHAIN - Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set. | 07-02-2015 |
| 20150214288 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and methods of forming the same are described. A semiconductor arrangement includes a first tier including a first capacitor, a second tier over the first tier, the second tier including a second capacitor, and a first substrate between the first tier and the second tier. The first capacitor is connected to the second capacitor through the substrate. A plurality of tiers are contemplated, such that a total capacitance of the semiconductor arrangement increases based upon interconnection of metal layers of different tiers. Additionally, the semiconductor arrangement has a greater area efficiency as compared to multiple capacitors in parallel. | 07-30-2015 |
| 20160091563 | SCAN FLIP-FLOP - A pull cell scan flip-flop includes a scan flip-flop and a pull cell. The pull cell is configured to receive a scan flip-flop output signal from the scan flip-flop, the scan flip-flop output signal having a scan flip-flop output value. The pull cell is configured to receive a scan-enable signal and to generate a modified flip-flop output signal. The modified flip-flop output signal has a specified fixed value responsive to the scan-enable signal having a first logic value, and the modified flip-flop output signal has the scan flip-flop output value responsive to the scan-enable signal having a second logic value. | 03-31-2016 |
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| 20120062447 | FLEXIBLE DISPLAY PANEL - A flexible display panel includes a flexible substrate, a plurality of pixels, a plurality of signal lines, a plurality of wave-like connecting lines, and a display medium. The flexible substrate has a plurality of display regions separated from one another and at least one foldable region located among the display regions. The pixels are disposed in the display regions. The signal lines are disposed on the flexible substrate and electrically connected to the pixels. The wave-like connecting lines are distributed in and across the foldable region. Each of the wave-like connecting lines is electrically connected to two of the signal lines adjacent to the wave-like connecting line. Each of the wave-like connecting lines across the foldable region has a wave-like pattern. The display medium is disposed on the flexible substrate to cover at least the display regions. | 03-15-2012 |
| 20120099072 | DISPLAY DEVICE - A display device includes a display panel and at least one driving chip. The display panel has a display region and a non-display region and includes a pixel array, a plurality of pads, a passivation layer, and a plurality of conductive patterns. The pixel array is located in the display region. The pads are located in the non-display region and electrically connected to the pixel array. The passivation layer is located on the pads and has a plurality of through holes. Each of the conductive patterns covers one of the pads and is electrically connected to the pad through at least one of the through holes. A material of the conductive patterns includes a polymer conductive material. The driving chip is located on the display panel and electrically connected to the pads of the display panel. | 04-26-2012 |
| 20120168790 | DISPLAY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - A display device structure includes an active device, a passivation layer, a pixel electrode and a first conductive material. The passivation layer covers the active device and has a first through hole exposing a portion of the active device. The pixel electrode is disposed on the passivation layer, and the pixel electrode is a non-thin-film electrode constituted by a plurality of micro-conductive structures. The first conductive material is filled in the first through hole and electrically connected to the exposed active device. The pixel electrode is electrically connected to the first conductive material. | 07-05-2012 |
| 20120193656 | DISPLAY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - A display device structure includes an active device, a passivation layer, a pixel electrode and a first conductive material. The passivation layer covers the active device and has a first through hole exposing a portion of the active device. The pixel electrode is disposed on the passivation layer, and the pixel electrode is a non-thin-film electrode consituted by a plurality of micro-conductive structures or includes an organic conductive polymer material. The first conductive material is disposed around the first through hole and electrically connected to the exposed active device. The pixel electrode is electrically connected to the first conductive material. | 08-02-2012 |
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| 20110178964 | Recommendation System Using Rough-Set and Multiple Features Mining Integrally and Method Thereof - The present invention solves problems of cold start, first rater, sparsity and scalability for recommendation. A recommendation system according to the present invention finds association rules through data mining. Then, the recommendation system integrates a rough-set algorithm and a statistical analysis prediction for recommendation. The recommendation is dynamically made from a result of the rough-set algorithm and a result of the statistical analysis prediction by setting a standard deviation as a threshold. | 07-21-2011 |
| 20110184948 | MUSIC RECOMMENDATION METHOD AND COMPUTER READABLE RECORDING MEDIUM STORING COMPUTER PROGRAM PERFORMING THE METHOD - A music recommendation method and a computer readable recording medium storing a computer program performing the method are provided. In the music recommendation method, music items and rating data matrix comprising ratings and user IDs are first provided. Then, the ratings of each music item are classified into positive ratings and negative ratings. Thereafter, a pre-processing phase comprising a frame-based clustering step and a sequence-based clustering step is performed to transform the music items into perceptual patterns. Then, a prediction phase is performed to determine an interest value of a plurality of target music items for an active user. Thereafter, the target music items arranged into a music recommendation list in accordance with the first interest value and the second interest values, wherein the music recommendation list is a reference for the active user to select one of the target items. | 07-28-2011 |
| 20120136896 | SYSTEM AND METHOD FOR IMPUTING MISSING VALUES AND COMPUTER PROGRAM PRODUCT THEREOF - A system and a method for imputing missing values and a computer program product thereof are applicable to a data matrix. The system includes a storage unit having the data matrix and a computing device. The computing device finds complete and incomplete data transactions from the data matrix, finds at least one target data transaction approximate to each incomplete data transaction from the complete data transactions, and obtains known data at corresponding positions to compute an initial estimated data to replace unknown data. Then, a correction data transaction containing the initial estimated data is selected from the incomplete data transactions, a rough set of the selected initial estimated data is found in a manner of grouping same data into one group, and a numerical value correlated to the initial estimated data is found and used to compute an imputed data, so as to impute the imputed data into the original estimated data. | 05-31-2012 |
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| 20130024824 | Optical Proximity Correction Method - An optical proximity correction method is provided. A target pattern is provided, and then the target pattern is decomposed to a first pattern and a second pattern. The first pattern and the second pattern are alternately arranged in a dense region. Then, a compensation pattern is provided and it is determined whether the compensation pattern is added into the first pattern to become a first revised pattern, or into the second pattern to become a second revised pattern. Finally, the first revised pattern is output onto a first mask and the second revised pattern is output onto a second mask. | 01-24-2013 |
| 20130280645 | Mask Set for Double Exposure Process and Method of Using the Mask Set - A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth. | 10-24-2013 |
| 20140256132 | METHOD FOR PATTERNING SEMICONDUCTOR STRUCTURE - A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask. | 09-11-2014 |
| 20140258946 | MASK SET FOR DOUBLE EXPOSURE PROCESS AND METHOD OF USING THE MASK SET - A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth. | 09-11-2014 |
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| 20120229199 | BANDGAP CIRCUIT AND START CIRCUIT THEREOF - A start circuit adapted to start a reference circuit including a plurality of bias nodes is provided. The start circuit includes a current source, a current minor, a load device, and a control device. The current source determines whether or not to generate an internal current according to a plurality of bias voltages on a part of the bias nodes. The current minor duplicates the internal current to produce a mirrored current. The load device adjusts a control voltage according to the mirrored current. The control device determines whether or not to generate a start voltage according to the control voltage, and transmits the start voltage to one of the part of the bias nodes, so as to break the reference circuit away from a zero-current state. | 09-13-2012 |
| 20130033301 | STRUCTURE OF OUTPUT STAGE - A structure of an output stage, and the structure includes a first electrode, a second electrode, a third electrode, a plurality of first auxiliary electrodes, a plurality of second auxiliary electrodes, a plurality of third auxiliary electrodes, a plurality of fourth auxiliary electrodes, a first switching unit, and a second switching unit. Wherein, a plurality of first currents flow through the turned-on first switching unit, and a first flowing direction of the first currents in the turned-on first switching unit is from the first electrode to the second electrode. A plurality of second currents flow through the turned-on second switching unit, and a second flowing direction of the second currents in the turned-on second switching unit is from the second electrode to the third electrode. | 02-07-2013 |
| 20130271231 | OSCILLATOR MODULE AND REFERENCE CIRCUIT THEREOF - A reference circuit for an oscillator module is provided. The reference circuit includes a reference voltage generation unit and a reference current generation unit. The reference voltage generation unit includes an electric element having a voltage proportional to absolute temperature (PTAT voltage) and provides a reference voltage based on the PTAT voltage. The reference current generation unit is coupled to the reference voltage generation unit and provides a reference current to the oscillator circuit to serve as an input current based on the PTAT voltage. The oscillator circuit generates a clock signal based on the reference voltage and the input current. The reference voltage and the input current are proportional to absolute temperature and have the same change trend relative to absolute temperature, such that the clock signal is a temperature insensitive signal. An oscillator module including an oscillator circuit and the foregoing reference circuit is also provided. | 10-17-2013 |
| 20130314835 | ADAPTIVE PROTECTION CIRCUIT MODULE FOR OPERATIONAL AMPLIFIER AND ADAPTIVE PROTECTION METHOD THEREOF - An adaptive protection circuit module for an operational amplifier including an over temperature protection circuit and an over current protection circuit is provided. The over temperature protection circuit provides a temperature protection function to power down the operational amplifier when an operating temperature of the operational amplifier increases higher than a first threshold temperature. The over current protection circuit provides a current protection function to limit an output current of the operational amplifier and adjusts the first threshold temperature to a second threshold temperature when the over current protection circuit is enabled. The second threshold temperature is lower than the first threshold temperature. After the first threshold temperature is adjusted to the second threshold temperature, the over temperature protection circuit powers down the operational amplifier when the operating temperature increases higher than the second threshold temperature. Furthermore, an adaptive protection method for the foregoing operational amplifier is also provided. | 11-28-2013 |
| 20140152375 | MULTIPLEXER AND DYNAMIC BIAS SWITCH THEREOF - A multiplexer and a dynamic bias switch thereof are provided. The dynamic bias switch includes a switch transistor and a dynamic bulk bias (DBB) unit. A first terminal and a second terminal of the switch transistor are respectively coupled to a first terminal and a second terminal of the dynamic bias switch. A bulk of the switch transistor is coupled to the DBB unit. The DBB unit selectively couples the first terminal or the second terminal of the switch transistor to the bulk of the switch transistor. | 06-05-2014 |
| 20140198421 | Over Temperature Protection Circuit - The present invention provides an over temperature protection circuit. The over temperature protection circuit includes a reference circuit and a hysteretic comparator. The reference circuit is used for generating a reference voltage and a changeable voltage. The changeable voltage is varied by temperature. The hysteretic comparator compares the reference voltage with the changeable voltage to output a power down signal. | 07-17-2014 |
| 20140361967 | VOLTAGE GENERATOR - A voltage generator for providing a plurality of output voltages having different levels includes: a reference block and a plurality of digital-to-analog conversion blocks. The reference block is employed for providing a plurality of reference voltages according to a supply voltage. The plurality of digital-to-analog conversion blocks is coupled to the reference block, and each of the digital-to-analog conversion blocks receives the reference voltages and generates a digital-to-analog output voltage according to a digital code, wherein digital-to-analog output voltages generated by the digital-to-analog conversion blocks have different levels, respectively. In addition, a range of the digital-to-analog output voltage generated by a first digital-to-analog conversion block of the digital-to-analog conversion blocks is different from that of the digital-to-analog output voltage generated by a second digital-to-analog conversion block. | 12-11-2014 |
| 20150339834 | Programmable Gamma Circuit for Gamma Correction - A programmable gamma circuit for gamma correction is disclosed. The programmable gamma circuit includes a string digital-to-analog converter, a first operational amplifier, and an output resistor string. The string digital-to-analog converter selects an analog voltage from a plurality of candidate voltages according to a digital reference code. An output terminal of the first operational amplifier outputs a first output voltage. A positive input terminal of the first operational amplifier is electrically connected to the string digital-to-analog converter for receiving the analog voltage. The output resistor string is divided into a first resistor part and a second resistor part by a connection terminal which is electrically connected to a negative input terminal of the first operational amplifier, and a resistance of the first resistor part is a multiple of a resistance of the second resistor part. | 11-26-2015 |
