Patent application number | Description | Published |
20130270559 | ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY - Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In sonic embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region. | 10-17-2013 |
20140001569 | HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS | 01-02-2014 |
20140084381 | PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE - Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively. | 03-27-2014 |
20140291737 | TRANSISTOR ARCHITECTURE HAVING EXTENDED RECESSED SPACER AND SOURCE/DRAIN REGIONS AND METHOD OF MAKING SAME - Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (L | 10-02-2014 |
20140308785 | PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE - Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively. | 10-16-2014 |
20140319623 | METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS - Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode. | 10-30-2014 |
20150179525 | HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS - High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers. | 06-25-2015 |
Patent application number | Description | Published |
20080220769 | Wake-on-WLAN for stationary wireless stations - Stationary wireless network stations are woken up using Wake-on-WLAN functionality. Wake-on-WLAN is provided by paging stations in a wireless network. Paging may support mobile stations across multiple access points. Paging may also support stationary nodes with reduced overhead. Wake-on-WLAN is also provided to stationary stations in idle mode by signifying a wake-on event in a traffic indication map (TIM). Wake-on events may occur when a station is associated or disassociated with an access point. Upon receiving a wake-on event, a station associates or reassociates with an AP if necessary. | 09-11-2008 |
20080220770 | Wake-on-WLAN for stationary wireless stations - Stationary wireless network stations are woken up using Wake-on-WLAN functionality. Wake-on-WLAN is provided by paging stations in a wireless network. Paging may support mobile stations across multiple access points. Paging may also support stationary nodes with reduced overhead. Wake-on-WLAN is also provided to stationary stations in idle mode by signifying a wake-on event in a traffic indication map (TIM). Wake-on events may occur when a station is associated or disassociated with an access point. Upon receiving a wake-on event, a station associates or reassociates with an AP if necessary. | 09-11-2008 |
20080233962 | TECHNIQUES FOR ALWAYS ON ALWAYS CONNECTED OPERATION OF MOBILE PLATFORMS USING NETWORK INTERFACE CARDS - An embodiment of the present invention provides an apparatus, comprising a network interface (NIC) card operable in communication with a mobile platform to monitor network traffic and perform filtering to enable decreased system resource use in said mobile platform when in an Always On Always Connected (AOAC) state. | 09-25-2008 |
20080238794 | Configurable antenna for mixed wireless networks - Methods and apparatus to reconfigure an antenna for use with mixed wireless networks are described. In one embodiment, a switch is coupled between a first portion and a second portion of an antenna to cause the antenna to tune to a plurality of radio frequency bands. Other embodiments are also described. | 10-02-2008 |
Patent application number | Description | Published |
20090327986 | GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS - Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression. | 12-31-2009 |
20100185908 | Speed-Path Debug Using At-Speed Scan Test Patterns - Speed-path debug techniques based on at-speed scan test patterns. Potential speed paths are identified based upon detected at-speed scan pattern failures and unknown X-value simulation. When the number of identified speed paths is large, the suspect speed paths are ranked. | 07-22-2010 |
20100274518 | Diagnostic Test Pattern Generation For Small Delay Defect - Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs. | 10-28-2010 |
20120174049 | TIMING-AWARE TEST GENERATION AND FAULT SIMULATION - Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs. | 07-05-2012 |
20140047404 | TIMING-AWARE TEST GENERATION AND FAULT SIMULATION - Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs. | 02-13-2014 |
20140246705 | Programmable Leakage Test For Interconnects In Stacked Designs - Aspects of the invention relate to techniques of testing interconnects in stacked designs for leakage defects. Logic “1” or “0” is first applied to one end of an interconnect during a first pulse. Then, logic value at the one end is captured, which triggered by an edge of a second pulse. The first pulse precedes the second pulse by a time period being selected from a plurality of delay periods. The plurality of delay periods is generated by a device shared by a plurality of interconnects. | 09-04-2014 |
20140347088 | Method and Circuit Of Pulse-Vanishing Test - Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element. | 11-27-2014 |
20150323600 | TIMING-AWARE TEST GENERATION AND FAULT SIMULATION - Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs. | 11-12-2015 |
Patent application number | Description | Published |
20120310289 | FLEXIBLE PLATE FIXATION OF BONE FRACTURES - Embodiments provide methods, apparatuses, and systems for fixation of a fractured bone with a bone plate. In various embodiments, the systems and plates provide elastic suspension of the receiving holes relative to an osteosynthesis plate. This elastic suspension can promote load distribution between the screws that connect a bone segment to the plate, thereby reducing stress risers and load shielding effect. In addition, stress at the screw holes, and within the construct as a whole, is reduced by incorporation of these elastic elements in the plate. Additionally, in some embodiments where fracture healing by callus formation is desired, elastic suspension of the receiving holes relative to the osteosynthesis plate can enable small, controlled amounts of relative motion between bone fragments connected by the plate. This relative motion can promote fracture healing by callus formation. | 12-06-2012 |
20130204304 | BONE PLATE FOR ELASTIC OSTEOSYNTHESIS - Embodiments provide a method and device for plate osteosynthesis of a bone fracture that allows angle-stable fixation of the bone fracture, while permitting elastic axial motion at the fracture site in a controlled, symmetric manner to stimulate fracture healing. Embodiments pertain to a bone plate having an outer surface and a bone-facing surface. The bone plate incorporating internal sliding elements containing a threaded receiving hole for bone screws that have a correspondingly threaded screw head. The sliding elements undergo controlled displacement parallel to the longitudinal axis of the plate but are substantially constrained against displacement perpendicular to the longitudinal axis of the plate. The bone screws with threaded heads may be rigidly fixed to the threaded receiving holes in the sliding elements without compressing the bone plate onto the bone surface. Sliding elements are elastically suspended inside the bone plate and undergo dynamic motion. | 08-08-2013 |
20140330275 | FLEXIBLE PLATE FIXATION OF BONE FRACTURES - Embodiments provide methods, apparatuses, and systems for fixation of a fractured bone with a bone plate. In various embodiments, the systems and plates provide elastic suspension of the receiving holes relative to an osteosynthesis plate. This elastic suspension can promote load distribution between the screws that connect a bone segment to the plate, thereby reducing stress risers and load shielding effect. In addition, stress at the screw holes, and within the construct as a whole, is reduced by incorporation of these elastic elements in the plate. Additionally, in some embodiments where fracture healing by callus formation is desired, elastic suspension of the receiving holes relative to the osteosynthesis plate can enable small, controlled amounts of relative motion between bone fragments connected by the plate. This relative motion can promote fracture healing by callus formation. | 11-06-2014 |
20150025588 | FLEXIBLE PLATE FIXATION OF BONE FRACTURES - Embodiments provide methods, apparatuses, and systems for fixation of a fractured bone with a bone plate. In various embodiments, the systems and plates provide elastic suspension of the receiving holes relative to an osteosynthesis plate. This elastic suspension can promote load distribution between the screws that connect a bone segment to the plate, thereby reducing stress risers and load shielding effect. In addition, stress at the screw holes, and within the construct as a whole, is reduced by incorporation of these elastic elements in the plate. Additionally, in some embodiments where fracture healing by callus formation is desired, elastic suspension of the receiving holes relative to the osteosynthesis plate can enable small, controlled amounts of relative motion between bone fragments connected by the plate. This relative motion can promote fracture healing by callus formation. | 01-22-2015 |
20150030493 | POROUS STRUCTURES AND METHODS OF MAKING SAME - The present disclosure provides methods to improve the properties of a porous structure formed by a rapid manufacturing technique. Embodiments of the present disclosure increase the bonding between the micro-particles | 01-29-2015 |
20150327896 | FLEXIBLE PLATE FIXATION OF BONE FRACTURES - A device can be provided that includes a bone plate having an upper surface and a bone-facing surface, wherein the bone plate includes one or more openings extending through the bone plate from the upper surface to the bone-facing surface, and one or more sliding elements each including a fastener receiving hole. The one or more openings can at least partially surround a periphery of one of the receiving holes. Further, the one or more openings can be at least partially filled with an elastomer to support elastic suspension of the one or more sliding elements in the bone plate, thereby enabling relative displacement between the one or more sliding elements and the bone plate. At least one sensor can also be provided that is operable to assess a dynamic parameter of one of the one or more sliding elements within the bone plate. | 11-19-2015 |