Patent application number | Description | Published |
20130242757 | INTERCONNECTING SEGMENTED LAYER TWO NETWORK FOR CLOUD SWITCHING - In one embodiment, a layer-2 network that includes a cloud switch is partitioned into a plurality of segments, each segment including one or more cloud switch domains that are coupled via a logical port to a corresponding one of a plurality of internal logical shared media links. One of the internal logical shared media links is provisioned as a hub. One or more remaining internal logical shared media links are defaulted to be spokes. A spanning tree protocol (STP) is executed within each segment. The logical port of each cloud switch domain advertises a pseudo root bridge identifier (ID) to cause the internal logical shared media link to appear attached to a Root. The advertised pseudo root bridge ID of the hub is chosen to have a higher priority than the pseudo root bridge ID of the spokes to establish a hub and spoke relationship among the segments. | 09-19-2013 |
20130287038 | SYNCHRONIZATION OF TRAFFIC MULTIPLEXING IN LINK AGGREGATION - Synchronization of traffic multiplexing in link aggregation is described. In an embodiment, a first link aggregator and a second link aggregator are associated with a plurality of links. The first link aggregator maintains an identifier for each link indicating at least a state of enabled or disabled. A synchronized clock is established between the first link aggregator and the second link aggregator. A particular link of the plurality of links is transitioned. Wherein, the transitioning is performed by the first link aggregator sending, to the second link aggregator, a first message identifying a particular time to transition the particular link. The first link aggregator receives, from the second link aggregator, a second message indicating that the particular time is acceptable. In response to a determination that the second message indicates that the particular time is acceptable and that the synchronized clock has reached the particular time, transitioning the link. | 10-31-2013 |
20130336164 | SYSTEM AND METHOD FOR VIRTUAL PORTCHANNEL LOAD BALANCING IN A TRILL NETWORK - An example method includes storing a portion of virtual PortChannel (vPC) information in a TRansparent Interconnect of Lots of Links network environment, deriving, from the portion of vPC information, a physical nickname of an edge switch to which a frame can be forwarded, and rewriting an egress nickname in a TRILL header of the frame with the physical nickname. In example embodiments, the vPC information can include respective vPC virtual nicknames, EtherChannel hash algorithms, hash values, and physical nicknames of edge switches associated with vPCs in the network environment. In some embodiments, the portion of vPC information can be derived from an Interested vPC Type Length Value (TLV) information of an Intermediate System to Intermediate System (IS-IS) routing protocol data unit (PDU). | 12-19-2013 |
20140161131 | Flexible and Scalable Virtual Network Segment Pruning - A segment within a virtual network is identified as being supported by a segment bundling device. The segment within the virtual network supports a first host connected to a first bridging device and a second host connected to a second bridging device. The segment bundling device is used to receive virtual network address information describing the virtual network segmentation identifier (ID) for the segment used for receiving virtual network traffic for the first and second host. A segment bundling table associating a bundle ID with the virtual network segmentation identifier based on the upper ID and the lower ID of the virtual network ID is generated by the segment bundling device. The segment bundling device is used to distribute the segment bundling table to traffic forwarding devices in the virtual network that interface with the first bridging device and the second bridging device. | 06-12-2014 |
Patent application number | Description | Published |
20090201622 | Detachable electrostatic chuck for supporting a substrate in a process chamber - A substrate support has an electrostatic chuck comprising an electrostatic puck with a dielectric covering an electrode capable of being charged to energize a process gas. The chuck has a frontside surface to receive a substrate and a base plate having an annular flange. A spring loaded heat transfer plate contacts the base plate, and has a fluid channel comprising first and second spiral channels. A pedestal is below the heat transfer plate. | 08-13-2009 |
20100039747 | ELECTROSTATIC CHUCK ASSEMBLY - Embodiments of the present invention provide a cost effective electrostatic chuck assembly capable of operating over a wide temperature range in an ultra-high vacuum environment while minimizing thermo-mechanical stresses within the electrostatic chuck assembly. In one embodiment, the electrostatic chuck assembly includes a dielectric body having chucking electrodes which comprise a metal matrix composite material with a coefficient of thermal expansion (CTE) that is matched to the CTE of the dielectric body. | 02-18-2010 |
20100218785 | IN SITU PLASMA CLEAN FOR REMOVAL OF RESIDUE FROM PEDESTAL SURFACE WITHOUT BREAKING VACUUM - Methods and apparatus for in-situ plasma cleaning of a deposition chamber are provided. In one embodiment a method for plasma cleaning a deposition chamber without breaking vacuum is provided. The method comprises positioning a substrate on a susceptor disposed in the chamber and circumscribed by an electrically floating deposition ring, depositing a metal film on the substrate and the deposition ring in the chamber, grounding the metal film deposited on the deposition ring without breaking vacuum, and removing contaminants from the chamber with a plasma formed in the chamber without resputtering the metal film on the grounded deposition ring and without breaking vacuum. | 09-02-2010 |
20130285065 | PVD BUFFER LAYERS FOR LED FABRICATION - Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma. | 10-31-2013 |
20140196746 | IN SITU CHAMBER CLEAN WITH INERT HYDROGEN HELIUM MIXTURE DURING WAFER PROCESS - Embodiments of the present invention generally relate to a method for cleaning a processing chamber during substrate processing. During a first substrate processing step, a plasma is formed from a gas mixture of argon, helium, and hydrogen in the processing chamber. In a second substrate processing step, an argon plasma is formed in the processing chamber. | 07-17-2014 |
20140366912 | IN SITU PLASMA CLEAN FOR REMOVAL OF RESIDUE FROM PEDESTAL SURFACE WITHOUT BREAKING VACUUM - Methods and apparatus for in-situ plasma cleaning of a deposition chamber are provided. In one embodiment a method for plasma cleaning a deposition chamber without breaking vacuum is provided. The method comprises positioning a substrate on a susceptor disposed in the chamber and circumscribed by an electrically floating deposition ring, depositing a metal film on the substrate and the deposition ring in the chamber, grounding the metal film deposited on the deposition ring without breaking vacuum, and removing contaminants from the chamber with a plasma formed in the chamber without resputtering the metal film on the grounded deposition ring and without breaking vacuum. | 12-18-2014 |
20150146339 | PAD DESIGN FOR ELECTROSTATIC CHUCK SURFACE - Embodiments are directed to an electrostatic chuck surface having minimum contact area features. More particularly, embodiments of the present invention provide an electrostatic chuck assembly having a pattern of raised, elongated surface features for providing reduced particle generation and reduced wear of substrates and chucking devices. | 05-28-2015 |
Patent application number | Description | Published |
20130088808 | ELECTROSTATIC CHUCK - Embodiments of electrostatic chucks are provided herein. In some embodiments, an electrostatic chuck for retaining a substrate includes a base plate, a ceramic plate, supported by the base plate, having a substrate supporting surface, a first plurality of electrodes disposed within the ceramic plate having a first polarity, and a second plurality of electrodes disposed within the ceramic plate have a second polarity opposite from the first polarity, wherein the first and second plurality of electrodes are independently controllable to provide a desired chucking power and frequency. | 04-11-2013 |
20130088809 | ELECTROSTATIC CHUCK WITH TEMPERATURE CONTROL - Embodiments of an apparatus for controlling a temperature of an electrostatic chuck in a process chamber are provided herein. In some embodiments, the apparatus includes an electrostatic chuck disposed in a process chamber, the electrostatic chuck including a ceramic plate having a substrate supporting surface, and a cooling assembly including a plurality of cooling plates disposed below the electrostatic chuck to adjust the cooling capacity of the electrostatic chuck. In some embodiments, the plurality of cooling plates includes an inner cooling plate configured to control a temperature of a center portion of the electrostatic chuck, and an outer cooling plate configured to control a temperature of an outer portion of the electrostatic chuck. In some embodiments, the plurality of cooling plates includes an upper cooling plate that contacts a bottom surface of the electrostatic chuck, and a lower cooling plate which contacts a bottom surface of the upper cooling plate. | 04-11-2013 |
20140020629 | TWO PIECE SHUTTER DISK ASSEMBLY FOR A SUBSTRATE PROCESS CHAMBER - Shutter disk assemblies for use in process chambers to protect a substrate support disposed below the shutter disk assembly from undesired material deposition are provided herein. In some embodiments, a shutter disk assembly for use in a process chamber to protect a substrate support disposed below the shutter disk assembly may include an upper disk member having a top surface and a bottom surface; and a lower carrier member having at least a portion of the lower carrier member disposed below a portion of the upper disk member to support the upper disk member and to create a protective overlap region that prevents exposure of the substrate support upon deformation of the upper disk member. | 01-23-2014 |
20140196848 | FINNED SHUTTER DISK FOR A SUBSTRATE PROCESS CHAMBER - Shutter disks for use in process chambers are provided herein. In some embodiments, a shutter disk for use in a process chamber may include a body having an outer perimeter, a top surface of the body, wherein the top surface includes a central portion having a substantially horizontal planar surface, and at least one angled structure disposed radially outward of the central portion, each of the at least one angled structure having a top portion and an angled surface disposed at a downward angle in a radially outward direction from the top portion toward the outer perimeter, and a bottom surface of the body. | 07-17-2014 |
20140262043 | SUBSTRATE SUPPORT FOR PLASMA ETCH OPERATIONS - Methods and apparatus for processing substrates are disclosed herein. In some embodiments, a substrate support to support a substrate in a processing chamber includes a dielectric insulator plate; a conductive plate supported on the dielectric insulator plate, the conductive plate comprising a top surface and a bottom surface defining a thickness between the top surface and the bottom surface, wherein an edge portion of the conductive plate tapers in a radially outward direction; and a dielectric plate comprising a substrate support surface disposed upon the top surface of the conductor plate. | 09-18-2014 |
Patent application number | Description | Published |
20120327766 | LEVEL OF HIERARCHY IN MST FOR TRAFFIC LOCALIZATION AND LOAD BALANCING - In one embodiment, a multiple spanning tree (MST) region is defined in a network, where the MST region includes a plurality of network nodes interconnected by links. A MST cluster is defined within the MST region, where the MST cluster includes a plurality of network nodes selected from the plurality of network nodes of the MST region. A network node of the MST cluster generates one or more MST bridge protocol data units (BPDUs) that present the MST cluster as a single logical entity to network nodes of the MST region that are not included in the MST cluster, yet enables per-multiple spanning tree instance (per-MSTI) load balancing of traffic across inter-cluster links that connect network nodes included in the MST cluster and network nodes of the MST region that are not included in the MST cluster. | 12-27-2012 |
20140050116 | Techniques for Generic Pruning in a Trill Network - Techniques are provided for managing and distributing communications in a network. At a first switch device arranged in a first configuration in a network, a set of one or more network attributes are determined, which are associated with network communications that the first switch device is interested in receiving from other network devices. The first switch device sends to a controller device an attribute interest message that informs the controller device of the set of network attributes. The first switch device receives a mapping of the network attributes in to one or more identifiers. The identifiers are included in a header of subsequent frames sent in the network. An identifier interest message is then sent to a second switch device arranged in a second network configuration in the network to inform the second switch device of identifiers of the network attributes of which the first device has an interest. | 02-20-2014 |
20140050217 | Two-Stage Port-Channel Resolution in a Multistage Fabric Switch - In some embodiments, a data packet may be received at a leaf switch. A port-channel associated with a destination port for the data packet may be identified, and the data packet may be transmitted to the destination port via the identified port-channel. | 02-20-2014 |
20140101302 | Techniques for Scalable and Foolproof Virtual Machine Move Handling with Virtual Port Channels - Techniques are provided for managing movements of virtual machines in a network. At a first switch, a virtual machine (VM) is detected. The VM is hosted by a physical server coupled to the first switch. A message is sent to other switches and it indicates that the VM is hosted by the physical server. When the first switch is paired with a second switch as a virtual port channel (vPC) pair, the message includes a switch identifier that identifies the second switch. A receiving switch receives the message from a source switch in the network comprising a route update associated with the VM. A routing table of the receiving switch is evaluated to determine whether the host route is associated with a server facing the physical port. The message is examined to determine it contains the switch identifier. | 04-10-2014 |
20140177640 | Intelligent Host Route Distribution for Low Latency Forwarding and Ubiquitous Virtual Machine Mobility in Interconnected Data Centers - Techniques are presented for distributing host route information of virtual machines to routing bridges (RBridges). A first RBridge receives a routing message that is associated with a virtual machine and is sent by a second RBridge. The routing message comprises of mobility attribute information associated with a mobility characteristic of the virtual machine obtained from an egress RBridge that distributes the routing message. The first RBridge adds a forwarding table attribute to the routing message that indicates whether or not the first RBridge has host route information associated with the virtual machine in a forwarding table of the first RBridge. The first RBridge also distributes the routing message including the mobility attribute information and the forwarding table attribute, to one or more RBridges in the network. | 06-26-2014 |
20150085859 | Two-Stage Port-Channel Resolution in a Multistage Fabric Switch - In some embodiments, a data packet may be received at a leaf switch. A port-channel associated with a destination port for the data packet may be identified, and the data packet may be transmitted to the destination port via the identified port-channel. | 03-26-2015 |
20150103841 | Intelligent Host Route Distribution for Low Latency Forwarding and Ubiquitous Virtual Machine Mobility in Interconnected Data Centers - Techniques are presented for distributing host route information of virtual machines to routing bridges (RBridges). A first RBridge receives a routing message that is associated with a virtual machine and is sent by a second RBridge. The routing message comprises of mobility attribute information associated with a mobility characteristic of the virtual machine obtained from an egress RBridge that distributes the routing message. The first RBridge adds a forwarding table attribute to the routing message that indicates whether or not the first RBridge has host route information associated with the virtual machine in a forwarding table of the first RBridge. The first RBridge also distributes the routing message including the mobility attribute information and the forwarding table attribute, to one or more RBridges in the network. | 04-16-2015 |
Patent application number | Description | Published |
20130301407 | METHOD AND APPARATUS FOR ADAPTIVE FAST START IN LINK AGGREGATION - In one embodiment, a period between periodic transmissions of protocol data units (PDUs) used to form or maintain a link aggregation group is initially set to a fixed value. When a stress condition is detected, the period between periodic transmissions of PDUs is increased from the initial value. When the stress condition is determined to have eased, the period between periodic transmissions of PDUs is reduced back toward the fixed value. | 11-14-2013 |
20130301427 | GRACE STATE AND PACING IN LINK AGGREGATION - In one embodiment, one or more indicia of stress are monitored. Based on the one or more indicia of stress, it is determined a stress condition exists. In response to the stress condition, one or more link aggregation actors and partners are caused to enter a grace state for a grace period. While the one or more link aggregation actors and partners are in the grace state, link aggregation formation is paced on a plurality of links by delaying formation of one or more new link aggregation groups on the plurality of links until a hold is released. Upon expiration of the grace period, the grace state is exited. | 11-14-2013 |
20140056178 | TRILL OPTIMAL FORWARDING AND TRAFFIC ENGINEERED MULTIPATHING IN CLOUD SWITCHING - In one embodiment, a plurality of leaf switches that include host facing ports are configured as a cloud switch. An indication of connectivity between the leaf switches of the cloud switch and routing bridges (RBridges) external to the cloud switch may be added to link state packets (LSPs) sent over the at least one logical shared media link. A lookup table may be generated that specifies next hop leaf switches. The generated lookup table may be used to forward frames to one or more particular nexthop leaf switches. Further, traffic engineering parameters may be collected. Equal cost multipath (ECMP) nexthop leaf switches and distribution trees to reach one or more destinations may be examined. Traffic may be distributed across ones of them based on the traffic engineering parameters. | 02-27-2014 |
20140064150 | MST EXTENSIONS FOR FLEXIBLE AND SCALABLE VN-SEGMENT LOOP PREVENTION - In one embodiment, a first number of multiple spanning tree instances (MSTIs) are defined within a network. A second number of network segments associated with segmentation identifier (IDs) are also configured, where the first number of MSTIs is less than the second number of segmentation IDs. Segmentation ID to MSTI mappings are maintained that map each defined segmentation ID of the second number of network segments to one of the first number of MSTIs. A segmentation mapping digest is computed of the segmentation ID to MSTI mappings. Multiple spanning tree (MST) bridge protocol data units (BPDUs) are broadcast that include the digest of the segmentation ID to MSTI mappings. | 03-06-2014 |
20140198800 | MSDC SCALING THROUGH ON-DEMAND PATH UPDATE - In one embodiment, a copy of an original packet of a traffic flow is created at an ingress leaf node of a cloud switch. The ingress leaf node forwards the original packet along a less-specific path through the cloud switch, the less-specific path based on a domain index of an egress domain for the original packet. The copy of the original packet is modified to create a more specific path learn request packet. The ingress leaf node forwards the more specific path learn request packet along the less-specific path through the cloud switch. The ingress leaf node received back a more specific path learn request reply packet that includes an indication of a fabric system port. The ingress leaf node then programs a forwarding table based on the indication of the fabric system port, to have subsequent packets of the traffic flow forwarded along a more-specific path. | 07-17-2014 |
20150117188 | METHOD AND APPARATUS FOR ADAPTIVE FAST START IN LINK AGGREGATION - In one embodiment, a period between periodic transmissions of protocol data units (PDUs) used to form or maintain a link aggregation group is initially set to a fixed value. When a stress condition is detected, the period between periodic transmissions of PDUs is increased from the initial value. When the stress condition is determined to have eased, the period between periodic transmissions of PDUs is reduced back toward the fixed value. | 04-30-2015 |
Patent application number | Description | Published |
20130024580 | Transient Unpruning for Faster Layer-Two Convergence - In one embodiment, a method includes detecting a change in network topology and broadcasting a transient unconditional unpruning message to all nodes in the network. The message is configured to instruct each network element receiving the message to start a phase timer in response to the broadcast message; unprune its operational ports; and, upon expiration of the phase timer, prune its ports in accordance with the results of a pruning protocol. | 01-24-2013 |
20140092780 | METHODS AND APPARATUSES FOR RAPID TRILL CONVERGENCE THROUGH INTEGRATION WITH LAYER TWO GATEWAY PORT - Methods and apparatuses for rapid TRILL convergence are disclosed herein. The methods can be implemented in a network including a plurality of RBridges or in a cloud network environment including a plurality of cloud switch domains. An example method for rapid TRILL convergence can include: Executing a spanning tree protocol (STP) for network topology in a network; and executing a Hello protocol for control and forwarding at the RBridge. The Hello protocol can be configured to elect a designated RBridge and assign an appointed forwarder. The method can also include assigning a transient appointed forwarder during a period of time between convergence of the STP and convergence of the Hello protocol. The transient appointed forwarder can be configured to forward frames in the network during the period of time between convergence of the STP and convergence of the Hello protocol. | 04-03-2014 |
20140101336 | SYSTEM AND METHOD FOR IMPLEMENTING A MULTILEVEL DATA CENTER FABRIC IN A NETWORK ENVIRONMENT - A method is provided in one example embodiment and includes determining whether a first network element with which a second network element is attempting to establish an adjacency is a client type element. If the first network element is determined to be a client type element, the method further includes determining whether the first and second network elements are in the same network area. If the first network element is a client type element and the first and second network elements are determined to be in the same network area, the adjacency is established. Subsequent to the establishing, a determination is made whether the first network element includes an inter-area forwarder (IAF). | 04-10-2014 |
20140254590 | SCALABLE MULTICAST ROUTE DISTRIBUTION IN A MULTITENANT DATA CENTER FABRIC IN A NETWORK ENVIRONMENT - A method is provided in one example embodiment and includes determining a route target (“RT”) membership for a network element; determining at least one attribute for the RT membership; and advertising the RT membership with the at least one attribute to other network elements. The at least one attribute may include an RT membership type attribute for indicating whether the RT membership is due to a local virtual network connection, transit support, or both. Additionally or alternatively, the at least one attribute may include a distribution tree binding attribute for indicating a distribution tree for the RT membership. | 09-11-2014 |
20140258485 | EFFICIENT HANDLING OF MULTI-DESTINATION TRAFFIC IN AN INTERNET PROTOCOL FABRIC DATA CENTER - A method is provided in one example embodiment and includes establishing at least one fixed topology distribution tree in a network, where the fixed topology distribution tree comprises one root node and a plurality of leaf nodes connected to the root node; maintaining at the root node an indication of multicast group interests advertised by the leaf nodes; and pruning traffic at the root node based on the advertised multicast group interests of the leaf nodes. In one embodiment, the root node is a spine switch and each of the leaf nodes is a leaf switch and each of the leaf nodes is connected to the root node by a single hop. | 09-11-2014 |
20140269695 | System for Conversational Link Aggregation Resolution in a Network Switch - Some implementations provide a method that includes: (i) receiving a list of logic link aggregations (LAGs) within a computer network, the list identifying a single physical egress port associated with each LAG; (ii) receiving a data unit; (iii) identifying that the data unit is addressed to a remote LAG included in the list of logic link aggregations; (iv) establishing a connection with the remote LAG; (v) downloading a detailed data describing the remote LAG from a control plane, the detailed data including a list of multiple available physical egress ports associated with the remote LAG, and; (vi) upon downloading the detailed data, incorporating the detailed data into the list of LAGs in association with an entry identifying the remote LAG. | 09-18-2014 |
20140344426 | Transient Unpruning for Faster Layer-Two Convergence - In one embodiment, a method includes detecting a change in network topology and broadcasting a transient unconditional unpruning message to multiple nodes in the network. The message is configured to instruct each of the nodes receiving the message to start a phase timer in response to the broadcast message; unprune its operational ports; and, upon expiration of the phase timer, prune its ports in accordance with the results of a pruning protocol. | 11-20-2014 |
20140348166 | OPTIMAL FORWARDING FOR TRILL FINE-GRAINED LABELING AND VXLAN INTERWORKING - An example method for determining an optimal forwarding path across a network having VxLAN gateways configured to implement both FGL networking and VxLAN capabilities can include learning RBridge nicknames associated with the VxLAN gateways in the network. Additionally, the method can include determining a path cost over the FGL network between each of the VxLAN gateways and a source node and a path cost over the VxLAN between each of the VxLAN gateways and a destination node. Further, the method can include determining an encapsulation overhead metric associated with the VxLAN and selecting one of the VxLAN gateways as an optimal VxLAN gateway. The selection can be based on the computed path costs over the FGL network and the VxLAN and the encapsulation overhead metric. | 11-27-2014 |
20140355475 | SYSTEM, DEVICES AND METHODS FOR FACILITATING COEXISTENCE OF VLAN LABELING AND FINE-GRAINED LABELING RBRIDGES - An example method for calculating a constrained distribution tree in a TRILL network including a plurality of VL and FGL RBridges can include learning an FGL multi-destination frame filtering capability of at least one of the FGL RBridges in the TRILL network, constructing a sub-graph including the FGL RBridges and associated links and calculating at least one sub-tree based on the sub-graph. The method can also include constructing a graph including VL RBridges, the FGL RBridges and associated links by adding links between the VL RBridges and the FGL RBridges. The FGL RBridge to which the VL RBridge is linked can have sufficient FGL multi-destination frame filtering capability. Further, the method can include calculating a constrained distribution tree based on the graph by treating the sub-tree as a logical node. | 12-04-2014 |
20150071286 | SYSTEM AND METHOD FOR UTILIZATION OF A SEGMENTATION IDENTIFICATION TO SUPPORT TRANSMISSION OF DATA TO A DESTINATION NODE - A method is provided in one example and includes receiving, at a receiving node, a packet that comprises information indicative of an internet protocol address and a segmentation identification, selecting a virtual routing and forwarding table corresponding with the segmentation identification, identifying a destination node based, at least in part, on the internet protocol address and the virtual routing and forwarding table, and transmitting the packet to the destination node. | 03-12-2015 |
20150139035 | Dynamic Virtual Port Instantiation for Scalable Multitenant Network - A leaf switch of a switch fabric includes multiple ports to connect with respective ones of multiple servers. Virtual local area networks (VLANs) are configured on the leaf switch. Dynamic creation of virtual ports is enabled on the leaf switch for at least one of the VLANs on an as needed basis. The leaf switch receives from a particular server connected to a corresponding one of the ports a notification message that a virtual machine is hosted on the particular server. Responsive to the notification message, the leaf switch dynamically creates a virtual port that associates the corresponding one of the ports with the at least one of the VLANs. | 05-21-2015 |
Patent application number | Description | Published |
20100161845 | METHOD AND SYSTEM FOR IMPROVING DIRECT MEMORY ACCESS OFFLOAD - A system for improving direct memory access (DMA) offload. The system includes a processor, a data DMA engine and memory components. The processor selects an executable command comprising subcommands. The DDMA engine executes DMA operations related to a subcommand to perform memory transfer operations. The memory components store the plurality of subcommands and status data resulting from DMA operations. Each of the memory components has a corresponding token associated therewith. Possession of a token allocates its associated memory component to the processor or the DDMA engine possessing the token, making it inaccessible to the other. A first memory component and a second memory component of the plurality of memory components are used by the processor and the DDMA engine respectively and simultaneously. Tokens, e.g., the first and/or the second, are exchanged between the DDMA engine and the processor when the DDMA engine and/or the microcontroller complete accessing associated memory components. | 06-24-2010 |
20100161941 | METHOD AND SYSTEM FOR IMPROVED FLASH CONTROLLER COMMANDS SELECTION - A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared. | 06-24-2010 |
20110145677 | METHOD AND SYSTEM FOR FAST TWO BIT ERROR CORRECTION - An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial. | 06-16-2011 |
20110161553 | MEMORY DEVICE WEAR-LEVELING TECHNIQUES - The wear-leveling techniques include discovering a persistent state of one or more memory devices, or building and caching persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for a given memory device. The techniques may also include processing memory access commands utilizing the cached persistent state parameters. When processing memory access commands, the logical block address and length parameter of a logical address of a command may be translated to a plurality of physical addresses for accessing one or more memory devices, each physical address includes a device address, a logical unit address, a block address, and a page address, wherein the block address includes one or more interleaved address bits. | 06-30-2011 |
20110161561 | VIRTUALIZATION OF CHIP ENABLES - Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device. | 06-30-2011 |
20120110242 | PROGRAMMABLE MEMORY CONTROLLER - A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device. | 05-03-2012 |
Patent application number | Description | Published |
20110052117 | INTEGRATED CIRCUIT WITH PINS AT MULTIPLE EDGES OF A CHIP - An improved integrated circuit (IC) layout is described that provides conductive pads on opposite sides of a substrate. The conductive pads provide for connectivity to the chip in different chip orientations. Accordingly, multiple chips having the same layout can be provided in a package, instead of providing each chip with a different layout. Since the same layout may be used for each chip, manufacturing costs are reduced. | 03-03-2011 |
20110148522 | INTEGRATED CIRCUIT HAVING A DUMMY TRANSIMPEDANCE AMPLIFIER - Consistent with the present disclosure, a “dummy” transimpedance amplifier (dummy TIA) is provided on a substrate along with one or more other transimpedance amplifiers (TIAs) that are connected to photodiodes and output voltage signals for further processing. Typically, the dummy TIA is not connected to a photodiode and does not supply a useful output. The dummy TIA, however, is subject to the same processing and temperature variations as the other TIAs, and, as a result, the voltage on the dummy TIA inverting input will be the same or substantially the same as that of the other TIAs. Thus, by sensing the dummy TIA inverting input voltage, an appropriate photodiode bias can be obtained without direct measurement of the voltage on the inverting inputs of the other TIAs. | 06-23-2011 |
20110150481 | ELECTRICAL RETURN-TO-ZERO (ERZ) DRIVER CIRCUIT - Consistent with the present disclosure, clock-and-data recovery (CDR) circuitry and driver circuitry are provided on a chip that is separate from the driver circuitry, thereby reducing the amount of power consumed by the driver circuitry and simplifying system design. In one example, timing of the ERZ signals is controlled by a feedback loop that adjusts the phase of a data carrying signal relative to a clock signal, such that the phase has a desired value. Timing of the ERZ signals may thus be adjusted to minimize errors. | 06-23-2011 |
20110293292 | Mitigating Signal Offsets in Optical Receivers - An optical receiver circuit is disclosed in which a number of electrical signals are processed to extract data encoded therein. The electrical signals may be compared during the process to selectively remove one or more waveforms from one or more corresponding electrical signals. Various data signals, each including one or more waveforms, may then be processed to extract the encoded data. The optical receiver circuit reduces, or eliminates, electrical offsets which may be present in one or more of the electrical signals to reduce corresponding errors in the encoded data signals. | 12-01-2011 |
Patent application number | Description | Published |
20100101602 | PLASMA CLEANING APPARATUS AND METHOD - Embodiments of the present invention generally include an apparatus for plasma cleaning and a method for plasma cleaning. Periodically, a PVD chamber may need to be cleaned to remove material that has built up in undesired locations within the chamber. Additionally, the sputtering target may need to be replaced. By removing the sputtering target and placing a grounded chamber lid in its place, the chamber may be plasma cleaned. The susceptor within the chamber may be electrically biased with an RF current. A stationary magnet assembly may be substantially centered behind the grounded lid to focus the cleaning plasma on the susceptor. Following the plasma cleaning, the magnet and lid may be removed and the sputtering target may be coupled to the chamber to continue processing. | 04-29-2010 |
20100101771 | HEATED COOLING PLATE FOR E-CHUCKS AND PEDESTALS - A method and apparatus for controlling the temperature of a substrate support assembly includes a pedestal, a chuck connected to the pedestal, a cooling plate structure thermally coupled with the chuck, a heater thermally coupled with the cooling plate structure, and a controller configured to control the cooling plate structure while controlling the heater during processing of a substrate on the chuck. The method includes cooling a substrate support with a cooling plate structure while heating the cooling plate structure with a heater thermally coupled with the cooling plate structure, monitoring the performance of the cooling plate structure and the heater, and regulating the performance of the cooling plate structure and the heater to maintain the substrate support at a desired temperature. | 04-29-2010 |
20140283872 | PLASMA CLEANING APPARATUS AND METHOD - Embodiments of the present invention generally include an apparatus for plasma cleaning and a method for plasma cleaning. Periodically, a PVD chamber may need to be cleaned to remove material that has built up in undesired locations within the chamber. Additionally, the sputtering target may need to be replaced. By removing the sputtering target and placing a grounded chamber lid in its place, the chamber may be plasma cleaned. The susceptor within the chamber may be electrically biased with an RF current. A stationary magnet assembly may be substantially centered behind the grounded lid to focus the cleaning plasma on the susceptor. Following the plasma cleaning, the magnet and lid may be removed and the sputtering target may be coupled to the chamber to continue processing. | 09-25-2014 |
Patent application number | Description | Published |
20140087668 | Methods and Apparatus for Performing Coexistence Testing for Multi-Antenna Electronic Devices - Radio frequency test systems for characterizing antenna performance in various radio coexistence scenarios are provided. In one suitable arrangement, a test system may be used to perform passive radio coexistence characterization. During passive radio coexistence characterization, at least one signal generator may be used to feed aggressor signals directly to antennas within an electronic device under test (DUT). The aggressor signals may generate undesired interference signals in a victim frequency band, which can then be received and analyzed using a spectrum analyzer. During active radio coexistence characterization, at least one radio communications emulator may be used to communicate with a DUT via a first test antenna. While the DUT is communicating with the at least one radio communications emulator, test signals may also be conveyed between DUT | 03-27-2014 |
20140167794 | Methods for Validating Radio-Frequency Test Stations - A manufacturing system for assembling wireless electronic devices is provided. The manufacturing system may include test stations for testing the radio-frequency performance of components that are to be assembled within the electronic devices. A reference test station may be calibrated using calibration coupons having known radio-frequency characteristics. The calibration coupons may include transmission line structures. The reference test station may measure verification standards to establish baseline measurement data. The verification standards may include circuitry having electrical components with given impedance values. Many verification coupons may be measured to enable testing for a wide range of impedance values. Test stations in the manufacturing system may subsequently measure the verification standards to generate test measurement data. The test measurement data may be compared to the baseline measurement data to characterize the performance of the test stations to ensure consistent test measurements across the test stations. | 06-19-2014 |
20140266941 | Electronic Device With Hybrid Inverted-F Slot Antenna - An electronic device may be provided with a housing. The housing may have a periphery that is surrounded by peripheral conductive structures such as a segmented peripheral metal member. A segment of the peripheral metal member may be separated from a ground by a slot. An antenna feed may have a positive antenna terminal coupled to the peripheral metal member and a ground terminal coupled to the ground and may feed both an inverted-F antenna structure that is formed from the peripheral metal member and the ground and a slot antenna structure that is formed from the slot. Control circuitry may tune the antenna by controlling adjustable components that are coupled to the peripheral metal member. The adjustable components may include adjustable inductors and adjustable capacitors. | 09-18-2014 |
20140302797 | Methods and Apparatus for Testing Electronic Devices Under Specified Radio-frequency Voltage and Current Stress - Test systems for characterizing devices under test (DUTs) are provided. A test system for testing a DUT in a shunt configuration may include a signal generator and a matching network that is coupled between the signal generator and the DUT and that is optimized to apply desired voltage/current stress to the DUT with reduced source power. The matching network may be configured to provide matching and desired stress levels at two or more frequency bands. In another suitable embodiment, a test system for testing a DUT in a series configuration may include a signal generator, an input matching network coupled between the DUT and a first terminal of the DUT, and an output matching network coupled between the DUT and a second terminal of the DUT. The input and output matching network may be optimized to apply desired voltage/current stress to the DUT with reduced source power. | 10-09-2014 |
20140329558 | Electronic Device With Multiple Antenna Feeds and Adjustable Filter and Matching Circuitry - Electronic devices may include antenna structures. The antenna structures may form an antenna having first and second feeds at different locations. A first transceiver may be coupled to the first feed using a first circuit. A second transceiver may be coupled to the second feed using a second circuit. The first and second feeds may be isolated from each other using the first and second circuits. The second circuit may have a notch filter that isolates the second feed from the first feed at operating frequencies associated with the first transceiver. The first circuit may include an adjustable component such as an adjustable capacitor. The adjustable component may be placed in different states depending on the mode of operation of the second transceiver to ensure that the first feed is isolated from the second feed. | 11-06-2014 |
20140333495 | Electronic Device Antenna With Multiple Feeds for Covering Three Communications Bands - Electronic devices may be provided that include radio-frequency transceiver circuitry and antennas. An antenna may be formed from an antenna resonating element and an antenna ground. The antenna resonating element may have a shorter portion that resonates at higher communications band frequencies and a longer portion that resonates at lower communications band frequencies. An extended portion of the antenna ground may form an inverted-F antenna resonating element portion of the antenna resonating element. The antenna resonating element may be formed from a peripheral conductive electronic device housing structure that is separated from the antenna ground by an opening. A first antenna feed may be coupled between the peripheral conductive electronic device housing structures and the antenna ground across the opening. A second antenna feed may be coupled to the inverted-F antenna resonating element portion of the antenna resonating element. | 11-13-2014 |
20140333496 | Antenna With Tunable High Band Parasitic Element - Electronic devices may be provided that include radio-frequency transceiver circuitry and antennas. An antenna may be formed from an antenna resonating element and an antenna ground. The antenna resonating element may have a shorter portion that resonates at higher communications band frequencies and a longer portion that resonates at lower communications band frequencies. The resonating element may be formed from a peripheral conductive electronic device housing structure that is separated from the antenna ground by an opening. A parasitic monopole antenna resonating element or parasitic loop antenna resonating element may be located in the opening. Antenna tuning in the higher communications band may be implemented using an adjustable inductor in the parasitic element. Antenna tuning in the lower communications band may be implemented using an adjustable inductor that couples the antenna resonating element to the antenna ground. | 11-13-2014 |
Patent application number | Description | Published |
20100309369 | ELECTRONIC DEVICE FLASH SHUTTER - An electronic device may have a camera module for acquiring still and video digital images of a subject. A light source such as a light-emitting diode may serve as a flash for the camera module. A shutter may be mounted above the light-emitting diode. When the light-emitting diode is not being used to produce a flash of light for illuminating the subject, the shutter may be closed to block the light-emitting diode from view by a user. During image acquisition operations in which it is desired to illuminate the subject, the shutter may be opened to allow light from the light-emitting diode to exit the electronic device. The electronic device may have a touch screen display with an active region and an inactive region. The camera module and light source may be mounted under a portion of the inactive region of the display. The shutter may include a filter structure. | 12-09-2010 |
20120257099 | DRIVER CIRCUIT FOR A CAMERA VOICE COIL MOTOR - A driver circuit for a camera voice coil motor (VCM) is described. A first power switch selectively conducts current from a VCM node to a power supply node, and a second power switch selectively conducts current from the VCM node to a power return node. A pulse width modulation circuit controls the first and second power switches. In another embodiment, a switch mode current control circuit sources VCM current alternately from the power supply node and the power return node, into the VCM node. Other embodiments are also described and claimed. | 10-11-2012 |
20140211081 | DRIVER CIRCUIT FOR A CAMERA VOICE COIL MOTOR - A driver circuit for a camera voice coil motor (VCM) is described. A first power switch selectively conducts current from a VCM node to a power supply node, and a second power switch selectively conducts current from the VCM node to a power return node. A pulse width modulation circuit controls the first and second power switches. In another embodiment, a switch mode current control circuit sources VCM current alternately from the power supply node and the power n node, into the VCM node. Other embodiments are also described and claimed. | 07-31-2014 |
20150070275 | SYSTEMS AND METHODS FOR NAVIGATING A SCENE USING DETERMINISTIC MOVEMENT OF AN ELECTRONIC DEVICE - Systems and methods are providing for scrolling the display of information based on the displacement of the electronic device. An electronic device can include a motion sensing component operative to detect movement of the electronic device (e.g., an accelerometer). The electronic device can display any suitable information, including information that is too large to display at a single instance on the display (e.g., a multi-page text document, or a large image). To view portions of the information that are not initially displayed (e.g., to scroll displayed information), the user can move the electronic device along the plane of the device. As the motion sensing component detects movement, the electronic device can scroll the displayed information to match the detected movement. In some embodiments, the electronic device can detect tilt movements and adjust the displayed information to reflect the tilted display. | 03-12-2015 |
20150085180 | DRIVER CIRCUIT FOR ELECTRO-ACTIVE POLYMER DEVICES - A driver circuit for electro-active polymer (EAP) device has a shared, voltage boost circuit that is coupled to drive a common terminal of first and second EAP devices to a given voltage. A first voltage boost circuit is coupled to drive a respective terminal of the first EAP device to an opposite polarity voltage, while a second voltage boost circuit is coupled to drive a respective terminal of the second EAP device to an opposite polarity voltage. Other embodiments are also described and claimed. | 03-26-2015 |
20150215534 | DRIVER CIRCUIT FOR A CAMERA VOICE COIL MOTOR - A driver circuit for a camera voice coil motor (VCM) is described. A first power switch selectively conducts current from a VCM node to a power supply node, and a second power switch selectively conducts current from the VCM node to a power return node. A pulse width modulation circuit controls the first and second power switches. In another embodiment, a switch mode current control circuit sources VCM current alternately from the power supply node and the power return node, into the VCM node. Other embodiments are also described and claimed. | 07-30-2015 |
Patent application number | Description | Published |
20120296782 | System for Managing Product Inventory Counts - A system for managing product inventory includes an Internet-connected server and software executing on the server from a non-transitory physical medium, the software providing establishment of a first association of at least one stock keeping unit (SKU) and any associated metadata including product availability counts to at least one point in time and or at least one time range identified within an interactive shopping media presentation, establishment of a second association of at least one potential consumer to the interactive shopping media presentation, monitoring for and tracking of interaction sequences initiated by the at least one potential consumer, the interaction sequences enabled from within the interactive shopping media presentation or from within an interactive display associated thereto, and adjustment of the SKU-based product availability counts in the SKU metadata relative to the latest interaction results. | 11-22-2012 |
20130110608 | Method for Incentivizing Network-Connected Consumers Patronizing a Network-Hosted Shopping Site | 05-02-2013 |
20130151352 | System Enabling Interactive In-Video Shopping from External Domains - A system for shopping includes, an Internet-connected server, and software executing on the server from a non-transitory physical medium, the software providing a first function for embedding, upon request, a machine-readable code into the source code of a remote webpage, the machine-readable code specifying a link to video player software and a link to at least one digital video file, and a second function for establishing at least one bidirectional communication session between a remote appliance connected to the webpage and a host server. | 06-13-2013 |