Patent application number | Description | Published |
20130109166 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CONTROLLED P-CHANNEL THRESHOLD VOLTAGE | 05-02-2013 |
20130270656 | REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES - The present disclosure is generally directed to various replacement gate structures for semiconductor devices. One illustrative gate structure disclosed herein includes, among other things, a gate insulation layer and a layer of gate electrode material with a substantially horizontal portion having a first thickness and a substantially vertical portion having a second thickness that is less than the first thickness. Furthermore, the substantially horizontal portion of the layer of gate electrode material is positioned adjacent to a bottom of the replacement gate structure and above at least a portion of the gate insulation layer, and the substantially vertical portion is positioned adjacent to sidewalls of the replacement gate structure. | 10-17-2013 |
20130323923 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING IMPROVED SPACERS - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer. | 12-05-2013 |
20130344692 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH FLUORINE PASSIVATION - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluorine-containing liquid is contacted with the high-k dielectric material and fluorine is incorporated into the high-k dielectric material. | 12-26-2013 |
20140242788 | METHOD OF FORMING A HIGH QUALITY INTERFACIAL LAYER FOR A SEMICONDUCTOR DEVICE BY PERFORMING A LOW TEMPERATURE ALD PROCESS - One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide. | 08-28-2014 |
Patent application number | Description | Published |
20080258219 | Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer - A semiconductor device is provided which comprises a semiconductor layer ( | 10-23-2008 |
20090075434 | METHOD OF REMOVING DEFECTS FROM A DIELECTRIC MATERIAL IN A SEMICONDUCTOR - A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N | 03-19-2009 |
20100035434 | PLASMA TREATMENT OF A SEMICONDUCTOR SURFACE FOR ENHANCED NUCLEATION OF A METAL-CONTAINING LAYER - A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of | 02-11-2010 |
20100230756 | SEMICONDUCTOR DEVICE WITH SELECTIVELY MODULATED GATE WORK FUNCTION - A semiconductor device is provided which comprises a semiconductor layer ( | 09-16-2010 |
20110237073 | METHOD FOR FORMING A THROUGH SILICON VIA (TSV) - A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer. | 09-29-2011 |
Patent application number | Description | Published |
20130224927 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH NARROW, METAL FILLED OPENINGS - Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode. | 08-29-2013 |
20140353733 | PROTECTION OF THE GATE STACK ENCAPSULATION - Semiconductor device structures at advanced technologies are provided, wherein a reliable encapsulation of a gate dielectric is already formed during very early stages of fabrication. In illustrative embodiments, a gate stack is formed over a surface of a semiconductor substrate and a sidewall spacer is formed adjacent to the gate stack for covering sidewall surfaces of the gate stack. An additional thin layer is formed over the sidewall spacer, the gate stack and the surface of the semiconductor substrate, and thereafter source/drain extension regions are implanted through the additional thin layer into the substrate in alignment with the sidewall spacer. | 12-04-2014 |
20150014813 | COMPLEX CIRCUIT ELEMENT AND CAPACITOR UTILIZING CMOS COMPATIBLE ANTIFERROELECTRIC HIGH-K MATERIALS - The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure. | 01-15-2015 |
20150179740 | TRANSISTOR DEVICE WITH STRAINED LAYER - A method for forming a transistor device is disclosed that includes forming a first gate electrode on a substrate, forming a nitride layer, in particular an SiN layer, over the first gate electrode and forming a first strained layer over the nitride layer, in particular the SiN layer. A transistor device is also disclosed that includes a first gate electrode, a nitride layer, in particular an SiN layer, formed over the first gate electrode and a first strained layer formed over the nitride layer, in particular the SiN layer. | 06-25-2015 |
20150214322 | SEMICONDUCTOR DEVICE WITH FEROOELECTRIC HAFNIUM OXIDE AND METHOD FOR FORMING SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device comprising a substrate, an undoped HfO | 07-30-2015 |
20150364535 | SEMICONDUCTOR STRUCTURE INCLUDING CAPACITORS HAVING DIFFERENT CAPACITOR DIELECTRICS AND METHOD FOR THE FORMATION THEREOF - An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material. | 12-17-2015 |