Patent application number | Description | Published |
20080219082 | NONVOLATILE SEMICONDUCTOR MEMORY - Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte. | 09-11-2008 |
20110051515 | NONVOLATILE SEMICONDUCTOR MEMORY - Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte. | 03-03-2011 |
20120218819 | NONVOLATILE SEMICONDUCTOR MEMORY - Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte. | 08-30-2012 |
Patent application number | Description | Published |
20100130083 | CATIONIC DYEABLE POLYURETHANE ELASTIC YARN AND METHOD OF PRODUCTION - Disclosed is a polyurethane elastic yarn which is excellent in elongation, resilience, heat resistance, alkali resistance, chemical resistance, and capability of being dyed with a cationic dye and which is suitable for use in a stretch cloth, a wearing apparel or the like. The polyurethane elastic yarn comprises: an elastic yarn comprising a polyurethane mainly composed of a polymer diol and a diisocyanate; and a polymer of a compound having a sulfonate group contained in the elastic yarn. | 05-27-2010 |
20100249285 | ELASTIC POLYURETHANE YARN AND PROCESS FOR PRODUCTION THEREOF - Disclosed is an elastic polyurethane yarn which can exhibit excellent heat resistance even when an unsaturated fatty acid or a heavy metal is attached to the yarn during dyeing at a high temperature, and which has high elastic recovery and high strength/elongation. Specifically disclosed is an elastic yarn comprising a polyurethane mainly composed of a polymer diol and a diisocyanate, which contains (a) a hindered phenol compound, (b) an N,N-dialkylsemicarbazide compound and (c) a nitrogenated aromatic compound, wherein the nitrogenated aromatic compound (c) is contained in an amount of 0.01 to 0.30 weight % inclusive. | 09-30-2010 |
20110033409 | DEODORANT MATERIAL - An object of the present invention is to provide a deodorant material having an excellent capability of removing an odor, especially a distinctive body odor of the middle-aged and elderly. The deodorant material comprises a polyurethane resin capable of removing the odor of nonenal, preferably further capable of removing the odor of at least one selected from the group consisting of ammonia, acetic acid, and isovaleric acid. | 02-10-2011 |
20120259074 | POLYURETHANE ELASTIC YARN AND PRODUCTION METHOD THEREOF - [Problem] To provide a polyurethane elastic yarn which has the high strength and ductility sought in polyurethane elastic yarn, and also has excellent durability and heat resistance, as well as little fatigue at low temperature; and a production method thereof. | 10-11-2012 |
20120296016 | POLYURETHANE ELASTIC YARN AND METHOD FOR PRODUCING SAME | 11-22-2012 |
20140087170 | ELASTIC FABRIC - To provide elastic fabric that has comfortable wear and fit even in thin and light fabric by using a high-powered polyurethane elastic fiber that has at least 1.5 times the active force and recovery per unit fineness at the time of 100 to 200% elongation compared to conventional polyurethane elastic fiber. Resolution means an elastic fabric comprising a polyurethane elastic fiber made of a polyol, with a molecular weight between 450 and 1600 with a ratio of weight average molecular weight to number average molecular weight of at least 1.8, an organic diisocyanate compound, and a diamine compound. | 03-27-2014 |
20140109280 | POLYURETHANE YARN, AS WELL AS FABRIC AND SWIMWEAR USING SAME - In order to provide a polyurethane yarn having exceptional performance in terms of resistance to chlorine embrittlement essentially without the use of zinc, which is a heavy metal, and having advantageous application particularly in swimwear; as well as a fabric and article of swimwear using the polyurethane yarn, the present invention is a polyurethane yarn characterized in containing a partially hindered phenol compound having at least one partially hindered hydroxyphenyl group and a molecular weight of 300 or more, and a synthetic carbonate comprising one metal selected from the group consisting of alkali metals and alkaline-earth metals. The polyurethane yarn and other fibers are combined to yield a fabric and article of swimwear. | 04-24-2014 |
20140148537 | ELASTIC POLYURETHANE THREAD AND MANUFACTURING METHOD THEREOF - In order to provide an elastic polyurethane thread with excellent antibacterial and deodorant properties as well as excellent color fastness, an elastic polyurethane thread is made which consists of polyurethanes which have polymer diols and diisocyanates as the starting materials, contains metallic phosphates in the range of 0.5-10 wt %, and has an emitted quantity of monoamine compounds with molecular weights of 120 or less of 100 μg/m | 05-29-2014 |
Patent application number | Description | Published |
20090052238 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more. | 02-26-2009 |
20100220531 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 09-02-2010 |
20110129826 | METHOD FOR DETERMINATION OF INFLAMMATORY DISEASE BY USING SINGLE NUCLEOTIDE POLYMORPHISM IN BRCA1-RELATED PROTEIN (BRAP) GENE - It is an object of the present invention to identify a novel single nucleotide polymorphism (SNP) associated with the development and advancement of inflammatory diseases such as myocardial infarction. The present invention provides a method for judging inflammatory diseases, which comprises detecting at least one gene polymorphism in the BRCA1-associated protein (BRAP) gene. | 06-02-2011 |
20110246860 | Semiconductor Integrated Circuit - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 10-06-2011 |
20120179953 | Semiconductor Integrated Circuit - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 07-12-2012 |
20130049099 | Semiconductor Device - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 02-28-2013 |
20130334592 | Semiconductor Device - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 12-19-2013 |
Patent application number | Description | Published |
20090010072 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 01-08-2009 |
20090122609 | SEMICONDUCTOR DEVICE - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 05-14-2009 |
20090213649 | Semiconductor processing device and IC card - A semiconductor processing device according to the invention includes a first non-volatile memory ( | 08-27-2009 |
20100038700 | Semiconductor Device - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 02-18-2010 |
20100157689 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 06-24-2010 |
20110211390 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided. | 09-01-2011 |
20110309428 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 12-22-2011 |
20120268981 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided. | 10-25-2012 |
20130235668 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 09-12-2013 |
20130277635 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided. | 10-24-2013 |
20140198577 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 07-17-2014 |
20140241051 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided. | 08-28-2014 |
Patent application number | Description | Published |
20080220420 | Method of Detecting Gene Polymorphism, Method of Diagnosing, Apparatus Therefor, and Test Reagent Kit - The object of the invention is to carry out typing for multiple SNP sites automatically from the stage of sample preparation. A mixture of sample ( | 09-11-2008 |
20080234509 | Stereoregular polymer and monomer thereof and process for production of both - An ester derivant having a crystal structure in which the molecules in two adjacent molecule planes are antiparallel is created from a carboxylic acid having carbon-carbon double bond and a compound having a functional group that can react to a carboxyl group of the carboxylic acid. The crystal of the ester derivant is then subjected to light irradiation or heating. | 09-25-2008 |
20080280293 | Method of Examining Inflammatory Disease and Method of Screening Remedy for Imflammatory Disease - A gene polymorphism on a Toll-like receptor gene is analyzed and an inflammatory disease is examined based on the results of the analysis. A remedy for an inflammatory disease is screened by selecting a substance capable of altering the interaction between Toll-like receptor and galectin-2. | 11-13-2008 |
20130022975 | METHOD FOR DETECTING ARTERIOSCLEROTIC DISEASES ON THE BASIS OF SINGLE NUCLEOTIDE POLYMORPHISM AT HUMAN CHROMOSOME 5P15.3 - An atherosclerotic disease such as myocardial infarction or angina pectoris is detected by analyzing a single nucleotide polymorphism on human chromosome 5p15.3, and by associating results of the analysis with the risk of the onset thereof. Examples of the single nucleotide polymorphism on human chromosome 5p15.3 include a nucleotide corresponding to the nucleotide at position 61 in the nucleotide sequence of SEQ ID NO: 1, SEQ ID NO: 2, or SEQ ID NO: 3, and a polymorphism at a nucleotide which is in linkage disequilibrium with the above nucleotide. | 01-24-2013 |
20140141987 | METHOD FOR DIAGNOSING ARRHYTHMIA BASED ON SINGLE NUCLEOTIDE POLYMORPHISM IN CHROMOSOME 1Q24, NEURL GENE, OR CUX2 GENE - A method for diagnosing arrhythmia such as atrial fibrillation is provided. A single nucleotide polymorphism present in the region 24 of the long arm of the chromosome 1, NEURL gene, or CUX2 gene is analyzed, and the risk of developing arrhythmia and/or the presence or absence of the onset of arrhythmia is diagnosed on the basis of the analysis result. | 05-22-2014 |